| 1. |
- Zou, Zhuo, et al.
(författare)
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An efficient passive RFID system for ubiquitous identification and sensing using impulse UWB radio
- 2007
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Ingår i: Elektrotechnik und Informationstechnik. - : Springer Science and Business Media LLC. - 0932-383X. ; 124:11, s. 397-403
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Tidskriftsartikel (refereegranskat)abstract
- The next generation RFID system for ubiquitous identification and sensing requires both energy and system efficiency. This paper describes an efficient passive RFID system using impulse ultra-wideband radio (IR-UWB), at a 10 m operation range. Unlike conventional passive RFID systems which rely on backscatter and narrowband radio, IR-UWB is introduced as the uplink (communication from a tag to a reader). By utilizing a specialized communication protocol and a novel ALOHA-based anti-collision algorithm, such semi-UWB systems enable a high network throughput (2000 tag/sec) under the low power and low cost constraint. A low power tag design for proof of concept is finally presented.
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| 2. |
- Amin, Yasar, et al.
(författare)
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Blueprint and integration of vastly efficient 802.11A WLAN front-end
- 2006
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Ingår i: WSEAS Transactions on Electronics. - 1109-9445. ; 3:4, s. 258-261
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Tidskriftsartikel (refereegranskat)abstract
- Next generation wireless communications terminals will demand the use of advanced component integration processes and high density packaging technologies in order to reduce size and to increase performance. This paper presents high density multilayer interconnects and integrated passives used to design high performance prototype filter for 5GHz wireless LAN receiver realized on MCM-D substrate. The thin film implementation of Multichip Module technology is identified as a useful platform for the integration of GaAs MMIC and silicon device technologies for microwave applications where performance, size and weight are critical factors. The ability of the MCM-D technology to provide controlled impedance, microstrip structures and integrated thin film passive components with useful performance in the microwave frequency regime has now been demonstrated.
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| 3. |
- Amin, Yasar, et al.
(författare)
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SoP design on liquid crystal polymer substrate for 5 GHz RF receiver front-end module
- 2005
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Ingår i: International Microelectronics and Packaging Society - 1st International Conference and Exhibition on Device Packaging 2005. - 9781604235722 ; , s. 236-240
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Konferensbidrag (refereegranskat)abstract
- Next generation wireless communications terminals will demand the use of advanced component integration processes and high density packaging technologies in order to reduce size and to increase performance. This paper presents highdensity multilayer interconnects and integrated passives used to design high performance prototype filter for 5GHz wireless LAN receiver realized on liquid crystal polymer (LCP) substrate. The thin film implementation of Multichip Module technology is identified as a useful platform for the integration of GaAs MMIC and silicon device technologies for microwave applications where performance, size and weight are critical factors. The ability of the MCM-D technology to provide controlled impedance, microstrip structures and integrated thin film passive components with useful performance in the microwave frequency regime has now been demonstrated.
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| 4. |
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| 5. |
- Ma, Ning, et al.
(författare)
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A 5Mgate/414mW Networked Media SoC in 0.13um CMOS with 720p Multi-Standard Video Decoding
- 2009
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Ingår i: 2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC). - : IEEE Solid-State Circuits Society. - 9781424444342 ; , s. 385-388
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Konferensbidrag (refereegranskat)abstract
- A flexible and high performance SoC is developed for networked media applications by integrating two RISC cores, Ethernet network interface and coarse-grained configurable video decoding unit. Real-time 1280x720@25fps MPEG-2/MPEG-4/RealVideo decoding is achieved for on-line video streams. The SoC is fabricated in 0.13um single-poly eight-metal CMOS technology with core size of 6.4mm * 6.4mm. To achieve low power design, flexible power management strategy is implemented for dynamically control of computational capabilities with various workloads. The maximum power consumption is 414mW at 1.2V supply voltage with the corresponding system frequency of 216MHz, when real-time HD (1280x720@25fps) video streams are decoded. When the SoC decodes real-time CIF (352x288@25fps) video streams, it requires 27MHz system frequency and consumes 95mW.
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| 6. |
- Niu, Yuechao, et al.
(författare)
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Design of a Digital Baseband Processor for UWB Transceiver on RFID Tag
- 2007
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Ingår i: 21st International Conference on Advanced Networking and Applications Workshops/Symposia, Vol 2, Proceedings. - : IEEE Computer Society. - 9780769528472 ; , s. 358-361
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Konferensbidrag (refereegranskat)abstract
- In this paper we present a novel digital baseband processor designed for UWB transceiver on RFID tag. It is a low power and low voltage (1.8V) full digital ASIC which is implemented in 0.18 mu m CMOS technology. The processor receives serial signals (consist of data and commands) from the RF Receiver, and based on received command carries out various functions such as receive data and write to the memory, compare data, send data, set/reset tag, kill tag and etc. The processor mainly consists of eight sub modules: Receive Buffer, Transmit Buffer, Random Number Generator (RNG), Slot Counter, Memory Controller, Reset Counter, Comparator, Controller.
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| 7. |
- Nurmi, T., et al.
(författare)
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Global interconnect analysis
- 2005
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Ingår i: Interconnect-Centric Design for Advanced SoC and NoC. - Boston : Springer Science+Business Media B.V.. - 9781402078354 - 9781402078361 ; , s. 55-84
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Bokkapitel (refereegranskat)abstract
- The rapid development in deep submicron (DSM) technology makes possible to design complex billion-transistor chips. To take full advantage of increased integration density and cope with the difficulties in designing such complex systems, the emphasis of design methodology has changed from gate-level design to the exploitation of intellectual property (IP) blocks. This IP-based design is rapidly becoming the dominating design paradigm in System-on-Chip (SoC) era. IP blocks themselves are usually verified by the supplier for some technology node but the problem is how to ensure the correct performance when the IP block is integrated in the SoC or even in Network-on-Chip (NoC) environment. The problems occur in adapting the block interface into the used communication frame. The main objective is to make computation (IP blocks) and communication independent on each other. Due to increasing integration density and diminishing wire dimensions, communication using traditional SoC interconnect schemes (such as buses) does not scale up properly compared with system complexity. This leads to the communication scheme where traditional buses and their arbitration are replaced with network switches connecting various IP blocks in different network nodes to each other. Thus, a shift from SoC to NoC is predicted when system complexity scales up on chip level. Network nodes bring inherent pipelining and buffering onto system level which is important when dealing with global wires that have more resistive and inductive nature in current and future DSM technologies. Additionally, undesired transmission errors can be reduced with errorchecking, e.g. in each network node. In this case, latency may increase as a result of increased reliability. In this chapter, we first discuss parasitic modeling in the presence of crosstalk and delay modeling of global wires. Inductance issues are discussed in more detail in chapter 5 and thus we omit them here. Some possible interconnect schemes in SoC and NoC are shortly discussed. In section 3.3 we evaluate cost functions (e.g. power consumption and area) that IP blocks set for the global communication network. We present a method how to evaluate those costs in the early phase of design. By evaluating costs of those resources we can better optimize global interconnects to meet both signal and power distribution challenges. We present one case study example on the cost evaluation. Finally, in section 3.4 we apply methods and theories presented in earlier sections and optimize global interconnects to meet different constraints. The delay in global wires is optimized using repeaters that are sized properly and placed in proper distances so that the overall delay is optimized. Then we present optimal signaling having maximum throughput as a constraint. Last, we present a case study in which both power and signal distribution are simultaneously optimized. This is done by using a method called interconnect partitioning and the design constraint in this case is the maximum allowed variation of power supply levels in the power distribution network. The variation depends on the grain size of the power distribution grid and power consumption taking place in IP (or functional) blocks due to simultaneous switching of large amount of logic gates in a very short time interval.
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| 8. |
- Pang, Zhibo, et al.
(författare)
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A Global Fresh Food Tracking Service Based on Novel Wireless Sensor and RFID Technologies
- 2009
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Konferensbidrag (refereegranskat)abstract
- A global fresh food tracking service is presented, in which a set of real-time primary environmental conditions for transport of fresh fruits and vegetables, including global position, temperature, relative humidity, concentrations of CO2, O2 and ethylene gases and 3-axis acceleration, is collected through mobile and remotely controllable wireless sensor nodes. Real time monitoring, tracking, alarming, close-loop controlling and information sharing could therefore be provided as WEB services with service oriental architecture. Fully functioned hardware modules, protocols and system software have been developed. A 50-day field test has been successfully carried out, proving the system concept and the robustness of hardware and software designed. Due to its worldwide deploy-ability and added-values to fresh food supply chain, it is now feasible to establish a practical fresh food tracking service business.
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| 9. |
- Pang, Zhibo, et al.
(författare)
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A Pervasive and Preventive Healthcare Solution for Medication Noncompliance and Daily Monitoring
- 2009
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Ingår i: 2009 2ND INTERNATIONAL SYMPOSIUM ON APPLIED SCIENCES IN BIOMEDICAL AND COMMUNICATION TECHNOLOGIES (ISABEL 2009). - NEW YORK : IEEE. - 9781424446407 ; , s. 315-320
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Konferensbidrag (refereegranskat)abstract
- Pervasive healthcare solution for medication noncompliance problem would help to save $177 billion annually in the United States. And the rapidly increasing demanding of daily monitoring with onsite diagnosis and prognosis is driving homecare solutions to integrate more and more sensing and data processing capacities. So a powerful system is needed not only to address the medication noncompliance but also to be used as a Pervasive Healthcare Station in home. In this paper, a pervasive and preventive healthcare solution for medication noncompliance and daily monitoring is proposed using an intelligent package sealed by Controlled Delamination Material (CDM) and controlled by Radio Frequency Identification (RFID). Onsite diagnosis and prognosis capacities for kinds of health parameters are supported due to scalable and intensive computing capacitance of the 2D-Mesh-NoC based multi-core architecture. Additionally, friendly human-machine interface is emphasized to make it usable for the elderly, disabled and patients due to enhanced multimedia performance. Experimental results of an implemented prototype confirmed the necessity of the multi-core architecture and approved the feasibility of the proposed intelligent package.
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| 10. |
- Rodriguez, Saul, et al.
(författare)
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A Novel BiST and Calibration Technique for CMOS Down-Converters
- 2008
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Ingår i: Circuits and Systems for Communications, 2008. ICCSC 2008. 4th IEEE International Conference on. - 9781424417070 ; , s. 828-832
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Konferensbidrag (refereegranskat)abstract
- This paper presents a new digital calibration methodology that allows CMOS Gilbert cell down-converters to meet their block specifications under large process, temperature and power supply variations. The calibration method consists of a novel built-in self test for direct conversion receivers that is able to measure the gain, and the second and third order intermodulation products of the mixer. A random optimizer algorithm based on a least square error function provides digital control of the biasing circuit and the loads of the mixer. The gain and IIP3 are calibrated by regulating the current of the input differential pair and by switching the loads. IIP2 calibration is achieved by using a novel technique that consists of offset voltages cancellation in the switching pairs. The technique is validated by calibrating a 0.18um CMOS mixer in several corner conditions.
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