| 1. |
- Khanzadi, M Reza, 1983, et al.
(författare)
-
Calculation of the Performance of Communication Systems from Measured Oscillator Phase Noise
- 2014
-
Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328 .- 1558-0806. ; 61:5, s. 1553-1565
-
Tidskriftsartikel (refereegranskat)abstract
- Oscillator phase noise (PN) is one of the major problems that affect the performance of communication systems. In this paper, a direct connection between oscillator measurements, in terms of measured single-side band PN spectrum, and the optimal communication system performance, in terms of the resulting error vector magnitude (EVM) due to PN, is mathematically derived and analyzed. First, a statistical model of the PN, considering the effect of white and colored noise sources, is derived. Then, we utilize this model to derive the modified Bayesian Cramer-Rao bound on PN estimation, and use it to find an EVM bound for the system performance. Based on our analysis, it is found that the influence from different noise regions strongly depends on the communication bandwidth, i.e., the symbol rate. For high symbol rate communication systems, cumulative PN that appears near carrier is of relatively low importance compared to the white PN far from carrier. Our results also show that 1/f^3 noise is more predictable compared to 1/f^2 noise and in a fair comparison it affects the performance less.
|
|
| 2. |
- Seyedhosseinzadeh, Neda, et al.
(författare)
-
A 100–140 GHz SiGe-BiCMOS sub-harmonic down-converter mixer
- 2017
-
Ingår i: 2017 12th European Microwave Integrated Circuits Conference (EuMIC). - 9782874870484
-
Konferensbidrag (refereegranskat)abstract
- This paper demonstrates a wideband, subharmonic down converting mixer using a commercial 130-nm SiGe-BiCMOS technology. The mixer adopts a frequency doubling LO-stage, a differential switched-transconductance RF-stage, on-chip LO and RF baluns, and two emitter-follower buffer-stages. The measured results exhibit a maximum conversion gain up to 2.6 dB over the frequency range of 100 to 140 GHz with a LO power of 5 dBm. The mixer achieves an input referred 1-dB compression point of −7.2 dBm, with a DC power of 46.3 mW, including 26.7 mW for buffer-stages. It demonstrates also up to 12 GHz 3-dB IF bandwidth, which to the authors' best knowledge, is the highest obtained among active sub-harmonic mixers operating above 100 GHz. The chip occupies 0.4 mm2, including pads.
|
|
| 3. |
- Chen, Jingjing, 1982, et al.
(författare)
-
10 Gbps 16QAM transmission over a 70/80 GHz (E-band) radio test-bed
- 2012
-
Ingår i: European Microwave Week 2012: "Space for Microwaves", EuMW 2012, Conference Proceedings - 7th European Microwave Integrated Circuits Conference, EuMIC 2012. - : IEEE. - 9782874870286 - 9781467323024 - 9782874870262 ; , s. 556-559
-
Konferensbidrag (refereegranskat)abstract
- A millimeter-wave radio test-bed is implemented which demonstrates 16QAM transmission over 70/80 GHz band for data rate up to 10 Gbps. Performance of the 16QAM transmitter and receiver is evaluated in a loop-back lab set-up. With the proposed 10 Gbps on single carrier system architecture, it is possible to achieve 40 Gbps over a 5 GHz bandwidth when combined with polarization and spatial multiplexing.
|
|
| 4. |
|
|
| 5. |
- Nopchinda, Dhecha, 1991, et al.
(författare)
-
8-PSK Upconverting Transmitter Using E-band Frequency Sextupler
- 2018
-
Ingår i: IEEE Microwave and Wireless Components Letters. - 1558-1764 .- 1531-1309. ; 28:2, s. 177-179
-
Tidskriftsartikel (refereegranskat)abstract
- Operation of a frequency sextupler (X6) as a radio frequency (RF) E-band upconverting transmitter is experimentally demonstrated. An 8-phase-shift keying signal is digitally upconverted to 13.1-GHz intermediate frequency (IF). The resulting signal then goes through the X6 resulting in IF-to-RF upconversion to 78.6 GHz without the need for high-frequency oscillator, mixer, or modulator. A simple one-sixth phase retardation of the baseband signal is used as digital predistortion. A full signal processing chain is implemented at the digital receiver. Techniques to mitigate remaining nonlinearity and worsened phase noise are considered.
|
|
| 6. |
- An, Sining, 1991, et al.
(författare)
-
A Synchronous Baseband Receiver for High-Data-Rate Millimeter-Wave Communication Systems
- 2019
-
Ingår i: IEEE Microwave and Wireless Components Letters. - 1558-1764 .- 1531-1309. ; 29:6, s. 412-414
-
Tidskriftsartikel (refereegranskat)abstract
- A novel synchronous baseband receiver is presented in this letter. With a pilot tone insertion at the transmitter, the proposed baseband receiver can perform carrier recovery (CR) regardless of modulation scheme and/or baud rate. The synchronous baseband receiver has an analog-digital hybrid structure, where a low-cost digital signal processor controls an analog local oscillator (LO) in frequency and phase to achieve CR. This structure requires only one low-cost analog-to-digital converter (ADC) with a sampling rate of 100 MS/s. A proof-of-concept demonstration at E-band achieves 9-Gb/s 64-quadratic-amplitude modulation (QAM) and 16-Gb/s QPSK transmissions.
|
|
| 7. |
- Bao, Mingquan, et al.
(författare)
-
A 135–183GHz Frequency Sixtupler in 250nm InP HBT
- 2020
-
Ingår i: IEEE MTT-S International Microwave Symposium Digest. - 0149-645X. ; 2020, s. 480-483
-
Konferensbidrag (refereegranskat)abstract
- A technique to design a broadband two-stage frequency tripler is proposed. The 1 st and the 2 nd harmonics obtained from the first stage are mixed in the second stage, getting the 3 rd harmonic. Between the two stages, there is a two-pole filter which lets the amplitude of the 1 st harmonic increase and the amplitude of the 2 nd harmonic decrease when the frequency increases. Consequently, a large 1 st harmonic is always mixed with a small 2 nd harmonic, and vice versa, which equalizes the amplitude of the mixing product, i.e., the 3 rd harmonic, over a large bandwidth. Together with a frequency doubler and a buffer amplifier, this frequency tripler is used in a frequency sixtupler. A proof-of-concept circuit is designed and implemented in 250 nm indium phosphide (InP) double-heterojunction bipolar transistor (DHBT) technology. For an input power of 6.3 dBm, the sixtupler has an output power between 0 dBm to 4.6 dBm in the output frequency range from 135 GHz to 183 GHz. It exhibits up to 13 dBc rejection ratio of the undesired 4 th , 5 th , and 7th harmonics. The sixtupler consumes a dc power of 100 mW, and achieves a peak power efficiency of 2.5%.
|
|
| 8. |
- Bao, M. Q., et al.
(författare)
-
A 110-to-147 GHz Frequency Sixtupler in a 130 nm Sige Bicmos Technology
- 2018
-
Ingår i: EuMIC 2018 - 2018 13th European Microwave Integrated Circuits Conference. ; , s. 105-108
-
Konferensbidrag (refereegranskat)abstract
- The presented D-band sixtupler consists of a frequency tripler, a frequency doubler, as well as amplifiers. The optimum arrangement for those blocks is investigated. The analysis shows that the tripler should precede the doubler. Furthermore, to extend the bandwidth, an amplifier with an increasing gain versus frequency is applied, to compensate the gain decrease of the tripler. This wideband frequency sixtupler is designed and characterized in a 130 nm SiGe BiCMOS technology. This sixtupler has a bandwidth of 37 GHz (from 110 to 147 GHz), the maximum output power is 4.5 dBm, with a DC power consumption of 310 mW. The maximum power efficiency is 0.9%.
|
|
| 9. |
- Carpenter, Sona, 1983, et al.
(författare)
-
A direct carrier I/Q modulator for high-speed communication at D-band using 130nm SiGe BiCMOS technology
- 2017
-
Ingår i: 2017 12th European Microwave Integrated Circuits Conference (EuMIC). - 9781538639665
-
Konferensbidrag (refereegranskat)abstract
- This paper presents a 110–170 GHz direct conversion I/Q modulator realized in 130 nm SiGe BiCMOS technology with ft/fmax values of 250 GHz/ 370 GHz. The design is based on double-balanced Gilbert mixer cells with on-chip quadrature LO phase shifter and RF balun. In single-sideband operation, the modulator exhibits up to 9.5 dB conversion gain and has measured 3 dB IF bandwidth of 12 GHz. The measured image rejection ratio and LO to RF isolation are as high as 20 dB and 31 dB respectively. Measured input P1dB is −17 dBm at 127 GHz output. The dc power consumption is 53 mW. The active chip area is 620 pm∗ 480 pm including the RF and LO baluns. The circuit is capable of transmitting more than 12 Gbit/s QPSK signal.
|
|
| 10. |
- Carpenter, Sona, et al.
(författare)
-
A Fully integrated D-band Direct-Conversion I/Q Transmitter and Receiver Chipset in SiGe BiCMOS Technology
- 2021
-
Ingår i: Journal of Communications and Networks. - 1976-5541 .- 1229-2370. ; 23:2, s. 73-82
-
Tidskriftsartikel (refereegranskat)abstract
- This paper presents design and characterization of single-chip 110-170 GHz (D-band) direct conversion in-phase/quadrature-phase (I/Q) transmitter and receiver monolithic microwave integrated circuits (MMICs), realized in a 130 nm SiGe BiCMOS process with ft/fmax of 250 GHz/370 GHz. The chipset is suitable for low power wideband communication and can be used in both homodyne and heterodyne architectures. The Transmitter chip consists of a six-stage power amplifier, an I/Q modulator, and a LO multiplier chain. The LO multiplier chain consists of frequency sixtupler followed by a two-stage amplifier. It exhibits a single sideband conversion gain of 23 dB and saturated output power of 0 dBm. The 3 dB RF bandwidth is 31 GHz from 114 to 145 GHz. The receiver includes a low noise amplifier, I/Q demodulator and x6 multiplier chain at the LO port. The receiver provides a conversion gain of 27 dB and has a noise figure of 10 dB. It has 3 dB RF bandwidth of 28 GHz from 112-140 GHz. The transmitter and receiver have dc power consumption of 240 mW and 280 mW, respectively. The chip area of each transmitter and receiver circuit is 1.4 mm x 1.1 mm.
|
|
