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A single-cycle outp...
A single-cycle output buffered router with layered switching for Networks-on-Chips
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Chen, Yancang (författare)
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- Lu, Zhonghai (författare)
- KTH,Elektroniksystem
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Xie, Lunguo (författare)
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Li, Jinwen (författare)
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Zhang, Minxuan (författare)
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(creator_code:org_t)
- Elsevier BV, 2012
- 2012
- Engelska.
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Ingår i: Computers & electrical engineering. - : Elsevier BV. - 0045-7906 .- 1879-0755. ; 38:4, s. 906-916
- Relaterad länk:
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https://urn.kb.se/re...
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https://doi.org/10.1...
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Abstract
Ämnesord
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- We present a single-cycle output buffered router based on layered switching for networks on chips (NoCs). Different from state-of-the-art NoC routers, the router has three important characteristics: (1) It employs layered switching, which implements wormhole on top of virtual cut-through (VCT) switching; (2) In contrast to input buffered architectures, it adopts an output buffered architecture; (3) It is single cycle, meaning that the router pipeline takes only one cycle for all flits. Experimental results show that the router achieves up to 80% of ideal network throughput under uniform random traffic pattern. Compared with wormhole switching, layered switching achieves up to 36.9% latency reduction for 12-flit packets under uniform random traffic with an injection rate of 0.5 flit/cycle/node. Under 65 nm technology synthesized results show that its critical path has only 20 logic gates, and it reduces 11% area compared to the input virtual-channel router with the same buffer capacity.
Ämnesord
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Nyckelord
- Microprocessor chips
- Network architecture
- Routers
- Switching
Publikations- och innehållstyp
- ref (ämneskategori)
- art (ämneskategori)
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