Towards stochastic delay bound analysis for network-on-chip

• We propose stochastic performance analysis in order to provide probabilistic quality-of-service guarantees in on-chip packet-switching networks. In contrast to deterministic analysis which gives per-flow absolute delay bound, stochastic analysis derives per-flow probabilistic delay bounding function, which can be used to avoid over-dimensioning network resources. Based on stochastic network calculus, we build a basic analytic model for an on-chip router, propose and exemplify a stochastic performance analysis flow. In experiments, we show the correctness and accuracy of our analysis, and exhibit its potential in enhancing network utilization with a relaxed delay requirement. Moreover, the benefits of such relaxation is demonstrated through a video playback application.

Ämnesord

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Nyckelord

Calculations

Microprocessor chips

Network-on-chip

Quality of service

Routers

Stochastic models

Stochastic systems

Switching networks

VLSI circuits

Analytic modeling

Bounding functions

Deterministic analysis

Net work utilization

Performance analysis

Quality of service guarantees

Stochastic analysis

Stochastic network calculus

Quality control

Publikations- och innehållstyp

ref (ämneskategori)

kon (ämneskategori)