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Non-Blocking Testin...
Non-Blocking Testing for Network-on-Chip
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Huang, Letian (författare)
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Wang, Junshi (författare)
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- Ebrahimi, Masoumeh (författare)
- KTH,Industriell och Medicinsk Elektronik
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- Daneshtalab, Masoud (författare)
- KTH,Elektronik och Inbyggda System
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Zhang, Xiaofan (författare)
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Li, Guangjun (författare)
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Jantsch, Axel (författare)
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(creator_code:org_t)
- IEEE, 2016
- 2016
- Engelska.
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Ingår i: IEEE Transactions on Computers. - : IEEE. - 0018-9340 .- 1557-9956. ; 65:3, s. 679-692
- Relaterad länk:
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https://urn.kb.se/re...
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https://doi.org/10.1...
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Abstract
Ämnesord
Stäng
- To achieve high reliability in on-chip networks, it is necessary to test the network as frequently as possible to detect physical failures before they lead to system-level failures. A main obstacle is that the circuit under test has to be isolated, resulting in network cuts and packet blockage which limit the testing frequency. To address this issue, we propose a comprehensive network-level approach which could test multiple routers simultaneously at high speed without blocking or dropping packets. We first introduce a reconfigurable router architecture allowing the cores to keep their connections with the network while the routers are under test. A deadlock-free and highly adaptive routing algorithm is proposed to support reconfigurations for testing. In addition, a testing sequence is defined to allow testing multiple routers to avoid dropping of packets. A procedure is proposed to control the behavior of the affected packets during the transition of a router from the normal to the testing mode and vice versa. This approach neither interrupts the execution of applications nor has a significant impact on the execution time. Experiments with the PARSEC benchmarks on an 8x8 NoC-based chip multiprocessors show only 3 percent execution time increase with four routers simultaneously under test.
Ämnesord
- NATURVETENSKAP -- Data- och informationsvetenskap -- Datavetenskap (hsv//swe)
- NATURAL SCIENCES -- Computer and Information Sciences -- Computer Sciences (hsv//eng)
Nyckelord
- Reconfigurable router architecture
- built-in self-test
- on-chip interconnect
- single-chip multiprocessors
Publikations- och innehållstyp
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- art (ämneskategori)
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