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Design and power op...
Design and power optimization of high-speed pipeline ADC for wideband CDMA applications
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Shi, C. L. (författare)
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Wu, Y. (författare)
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Lin, C. H. (författare)
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visa fler...
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Ismail, Mohammed (författare)
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visa färre...
- 2001
- 2001
- Engelska.
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Ingår i: Analog Integrated Circuits and Signal Processing. - 0925-1030 .- 1573-1979. ; 26:3, s. 229-238
- Relaterad länk:
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https://urn.kb.se/re...
Abstract
Ämnesord
Stäng
- This paper presents a 7-bit 64 MS/s pipeline A/D converter suitable for wideband CDMA applications. Targeting at achieving low power dissipation at high speed, techniques such as digital correction and optimal scaling of capacitor value have been employed. Switched-Opamp technique is used to further reduce power consumption. This ADC is implemented in 0.5 mum standard CMOS process. It operates from a single 3 V supply, and dissipates only 31 mW at 64 MS/s.
Nyckelord
- wideband CDMA
- pipeline
- A/D converter
- switched-opamp
- a/d converter
- cmos
- 10-b
Publikations- och innehållstyp
- ref (ämneskategori)
- art (ämneskategori)
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