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A Vernier Time-to-D...
A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture
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- Andersson, Niklas (författare)
- Linköpings universitet,Elektroniska Kretsar och System,Tekniska högskolan
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- Vesterbacka, Mark (författare)
- Linköpings universitet,Elektroniska Kretsar och System,Tekniska högskolan
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(creator_code:org_t)
- Institute of Electrical and Electronics Engineers (IEEE), 2014
- 2014
- Engelska.
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 61:10, s. 773-777
- Relaterad länk:
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https://liu.diva-por... (primary) (Raw object)
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https://urn.kb.se/re...
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https://doi.org/10.1...
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Abstract
Ämnesord
Stäng
- A new Vernier time-to-digital converter (TDC) architecture using a delay line and a chain of delay latches is proposed. The delay latches replace the functionality of one delay chain and the sample register commonly found in Vernier converters, hereby enabling power and hardware efficiency improvements. The delay latches can be implemented using either standard or full custom cells, allowing the architecture to be implemented in field-programmable gate arrays, digital synthesized application-specific integrated circuits, or in full custom design flows. To demonstrate the proposed concept, a 7-bit Vernier TDC has been implemented in a standard 65-nm CMOS process with an active core size of 33 mu m x 120 mu m. The time resolution is 5.7 ps with a power consumption of 1.75 mW measured at a conversion rate of 100 MS/s.
Ämnesord
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Nyckelord
- CMOS; delay latch; time-to-digital converter (TDC); Vernier
Publikations- och innehållstyp
- ref (ämneskategori)
- art (ämneskategori)
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