Trade-offs in low power multiplier blocks using serial arithmetic

• In this paper trade-offs in multiplier blocks are studied. Three different algorithms for realization of multiplier blocks are compared in terms of complexity, logic depth, and power consumption. A new algorithm that reduces the number of shifts while the number of adders is on average the same is presented. Hence, the total complexity is reduced for multiplier blocks implemented using serial arithmetic, where shift operations has a cost. The design of low power multiplier blocks is shown to be a more complicated problem than to reduce the complexity. A main factor that need to be considered is logic depth.

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