Sökning: onr:"swepub:oai:DiVA.org:miun-7568" >
Pseudo floating-gat...
Pseudo floating-gate design limitations in Nano-CMOS with low power supply
-
- Alfredsson, Jon (författare)
- Mittuniversitetet,Institutionen för informationsteknologi och medier (-2013),Electronics design division
-
- Aunet, Snorre (författare)
- Department of Informatics, University of Oslo
-
(creator_code:org_t)
- 2008
- 2008
- Engelska.
-
Ingår i: Proceedings of IFIP VLSI-SOC Conference 2008.
- Relaterad länk:
-
https://miun.diva-po... (primary) (Raw object)
-
visa fler...
-
https://urn.kb.se/re...
-
visa färre...
Abstract
Ämnesord
Stäng
- This paper shows simulation results from a recentlyproposed Pseudo Floating-Gate (PFG) technique for use insubthreshold. The design and simulations is performed in a 120nm process CMOS technology and show that there arelimitations that will make subthreshold PFG very difficult tomanufacture with full functionality. The simulations showlimitations in fan-in that will contribute to making it harder tomanufacture structures that have small area or a higharithmetic complexity per active element. It also showbandwidth limitations for the input and output signals.As a complement to the simulations of our PFG design we havealso made a summary of several different kinds of PFGtechniques that are previously developed and some of theirlimitations. The summary also tries to determine where thePFG techniques originates from and present an overview of themost obvious limitations they have.
Ämnesord
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Nyckelord
- low power digital cmos subthreshold floating-gate design
- Electrical engineering, electronics and photonics
- Elektroteknik, elektronik och fotonik
Publikations- och innehållstyp
- ref (ämneskategori)
- kon (ämneskategori)