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System and method f...
System and method for data classification and efficient virtual cache coherence without reverse translation
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- Davari, Mahdad (författare)
- Uppsala universitet,Datorteknik,UART
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- Ros, Alberto (författare)
- Uppsala universitet,Datorteknik,UART
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- Kaxiras, Stefanos (författare)
- Uppsala universitet,Datorteknik,UART
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(creator_code:org_t)
- 2013
- Engelska.
- Relaterad länk:
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https://urn.kb.se/re...
Abstract
Ämnesord
Stäng
- An on-chip memory hierarchy organization for a multicore processing system is disclosed. The hierarchy supports virtual- addressed private caches and a physical-addressed shared cache. The hierarchy classifies cache line data as private or shared to support a one-directional request response protocol. The classification can be determined from the generational behavior of a cache line in the private caches. Cache lines having a single generation in a private cache are Private, and cache lines having overlapping generations in two or more private caches are Shared. The Private or Shared classification is performed dynamically at run-time in hardware using a single translation lookaside buffer at the interface between the private and shared caches. The coherence protocol uses the data classification in a dynamic write policy for both shared data race free data and private data, differentiating in when data is put back to the shared cache based on the classification.
Ämnesord
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik -- Datorsystem (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering -- Computer Systems (hsv//eng)
Publikations- och innehållstyp
- pop (ämneskategori)
- pat (ämneskategori)