Sökning: onr:"swepub:oai:lup.lub.lu.se:13b0340e-dc8f-483e-a0e8-282a735b5ee9" >
Vertical III-V Nano...
Vertical III-V Nanowire Transistors for Low-Power Electronics
-
- Krishnaraja, Abinaya (författare)
- Lund University,Lunds universitet,Nanoelektronik,Forskargrupper vid Lunds universitet,LTH profilområde: AI och digitalisering,LTH profilområden,Lunds Tekniska Högskola,Nano Electronics,Lund University Research Groups,LTH Profile Area: AI and Digitalization,LTH Profile areas,Faculty of Engineering, LTH
-
(creator_code:org_t)
- ISBN 9789180397063
- 2023
- Engelska 127 s.
-
Serie: 1654-790X 1654-790X
- Relaterad länk:
-
https://portal.resea... (primary) (free)
-
visa fler...
-
https://lup.lub.lu.s...
-
visa färre...
Abstract
Ämnesord
Stäng
- Power dissipation has been the major challenge in the downscaling of transistor technology. Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) have struggled to keep a low power consumption while still maintaining a high performance due to the low carrier mobilities of Si but also due to their inherent minimum inverse subthreshold slope (S ≥ 60 mV/dec) which is limited by thermionic emission. This thesis work studied the capabilities and limitations of III-V based vertical nanowire n-type Tunneling Field-Effect Transistor (TFET) and p-type MOSFET (PMOS). InAs/InGaAsSb/GaSb heterojunction was employed in the whole study. The main focus was to understand the influence of the device fabrication processes and the structural factors of the nanowires such as band alignment, composition and doping on the electrical performance of the TFET. Optimizations of the device processes including spacer technology improvement, Equivalent Oxide Thickness (EOT) downscaling, and gate underlap/overlap were explored utilizing structural characterizations. Systematic fine tuning of the band alignment of the tunnel junction resultedin achieving the best performing sub-40 mV/dec TFETs with S = 32 mV/decand ION = 4μA/μm for IOFF = 1 nA/μm at VDS = 0.3 V. The suitability of employing TFET for electronic applications at cryogenic temperatures has been explored utilizing experimental device data. The impact of the choice of heterostructure and dopant incorporation were investigated to identify the optimum operating temperature and voltage in different temperature regimes. A novel gate last process self-aligning the gate and drain contacts to the intrinsic and doped segments, respectively was developed for vertical InGaAsSb-GaAsSb core-shell nanowire transistors leading to the first sub-100 mV/dec PMOS with S = 75 mV/dec, significant ION/ IOFF = 104 and IMIN < 1 nA/μm at VDS = -0.5 V.
Ämnesord
- TEKNIK OCH TEKNOLOGIER -- Nanoteknik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Nano-technology (hsv//eng)
Nyckelord
- metal-oxide-semiconductor field-effect transistor (MOSFET)
- Steep slope
- Tunnel Field-Effect Transistors
- Vertical nanowire
- III-V materials
- semiconducting III-V
- InAs
- GaSb
- InGaAsSb
- PMOS
- Transistor
- Electronics
Publikations- och innehållstyp
- dok (ämneskategori)
- vet (ämneskategori)
Hitta via bibliotek
Till lärosätets databas