Implementation of an area efficient crypto processor for a NB-IoT SoC platform

• This paper presents a cryptographic processor compliant with the security algorithms specified by the 3rd Generation Partnership Project (3GPP) specifications for Long Term Evolution (LTE). The proposed processor has been adapted to the needs of the low end portfolio technologies that compose the Internet of Things (IoT) market, which addresses low-Area, low-cost and low-data rate applications. The cryptographic processor has been described using the High-Level Synthesis (HLS) design flow and integrated with a CPU in a cycle accurate virtual platform. Various architectural optimizations are proposed in order to achieve a reduction of area ranging from 5% to 42% in comparison to similar work. In a 65-nm CMOS technology, the processor has a size of 53.6 kGE, and is capable of performing at 52.4 Mbps for the block cipher and 800 Mbps for the stream cipher algorithms at a 100 MHz clock.

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