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A 100-fJ/cycle Sub-...
A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS
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- Sherazi, Syed Muhammad Yasser (författare)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH
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- Nilsson, Peter (författare)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH
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- Sjöland, Henrik (författare)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH
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- Rodrigues, Joachim (författare)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH
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(creator_code:org_t)
- 2012
- 2012
- Engelska.
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Ingår i: 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012). - 9781467312615 - 9781467312615
- Relaterad länk:
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http://dx.doi.org/10...
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https://lup.lub.lu.s...
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https://doi.org/10.1...
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Abstract
Ämnesord
Stäng
- Measurements of a sub-threshold (sub-VT) decimation filter, composed of four half band digital (HBD) filters in 65 nm CMOS are presented. Different unfolded architectures are analyzed and implemented to combat speed degradation. The architectures are analyzed for throughput and energy efficiency over several threshold options. Reliability in the sub-VT domain is analyzed by Monte-Carlo simulations. The simulation results are validated by measurements and demonstrate that low-power standard threshold logic (LP-SVT) and different architectural flavors are suitable for a low-power implementation. Silicon measurements prove functionality down to 350mV supply, with a maximum clock frequency of 500 kHz, having an energy dissipation of 102 fJ/cycle.
Ämnesord
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Nyckelord
- energy dissipation
- measurements
- sub-threshold
- half band digital (HBD) filters
- 65 nm CMOS
- and architectures.
Publikations- och innehållstyp
- kon (ämneskategori)
- ref (ämneskategori)
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