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Low-temperature bac...
Low-temperature back-end-of-line technology compatible with III-V nanowire MOSFETs
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- Andric, Stefan (författare)
- Lund University,Lunds universitet,Nanoelektronik,Forskargrupper vid Lunds universitet,Nano Electronics,Lund University Research Groups
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- Ohlsson Fhager, Lars (författare)
- Lund University,Lunds universitet,Nanoelektronik,Forskargrupper vid Lunds universitet,Nano Electronics,Lund University Research Groups
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- Lindelöw, Fredrik (författare)
- Lund University,Lunds universitet,NanoLund: Centre for Nanoscience,Annan verksamhet, LTH,Lunds Tekniska Högskola,Nanoelektronik,Forskargrupper vid Lunds universitet,Other operations, LTH,Faculty of Engineering, LTH,Nano Electronics,Lund University Research Groups
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- Kilpi, Olli Pekka (författare)
- Lund University,Lunds universitet,Nanoelektronik,Forskargrupper vid Lunds universitet,Nano Electronics,Lund University Research Groups
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- Wernersson, Lars Erik (författare)
- Lund University,Lunds universitet,Nanoelektronik,Forskargrupper vid Lunds universitet,Nano Electronics,Lund University Research Groups
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(creator_code:org_t)
- American Vacuum Society, 2019
- 2019
- Engelska.
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Ingår i: Journal of Vacuum Science and Technology B: Nanotechnology and Microelectronics. - : American Vacuum Society. - 2166-2746 .- 2166-2754. ; 37:6
- Relaterad länk:
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http://dx.doi.org/10...
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https://lup.lub.lu.s...
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https://doi.org/10.1...
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Abstract
Ämnesord
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- We present a low-temperature processing scheme for the integration of either lateral or vertical nanowire (NW) transistors with a multilayer back-end-of-line interconnect stack. The nanowire device temperature budget has been addressed, and materials for the interconnect fabrication have been selected accordingly. A benzocyclobutene (BCB) polymer is used as an interlayer dielectric, with interconnect vias formed by reactive ion etching. A study on via etching conditions for multiple interlayer dielectric thicknesses reveals that the sidewall slope can be engineered. An optimal reactive ion etch is identified at 250 mTorr chamber pressure and power of 160 W, using an SF6 to O2 gas mix of 4%. This results in a low via resistance, even for scaled structures. The BCB dielectric etch rate and dielectric-to-soft mask etch selectivity are quantified. Electrical measurements on lateral and vertical III-V NW transistors, before and after the back-end-of-line process, are presented. No performance degradation is observed, only minor differences that are attributed to contact annealing and threshold voltage shift.
Ämnesord
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik -- Kommunikationssystem (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering -- Communication Systems (hsv//eng)
- TEKNIK OCH TEKNOLOGIER -- Nanoteknik -- Nanoteknik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Nano-technology -- Nano-technology (hsv//eng)
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