Stacking of heterostructures and metallic elements for a submicron resonant tunneling transistor

• We have successfully embedded a metal gate in-between two resonant tunneling double barrier heterostructures (RTD), thus realizing a three dimensional resonant tunneling transistor. The gate is placed 30 nm above and 100 below the two RTD's, respectively. The asymmetric gate allows for a unique control of the current-voltage characteristics, not only controlling the peak current but also the peak voltage. We have modeled the transistor with Cadence, a standard simulation package for circuit simulations, achieving good agreement with experimental data

Ämnesord

NATURVETENSKAP  -- Fysik -- Den kondenserade materiens fysik (hsv//swe)

NATURAL SCIENCES  -- Physical Sciences -- Condensed Matter Physics (hsv//eng)

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Nyckelord

circuit simulations

peak voltage

simulation package

stacking

peak current

heterostructures

metallic elements

submicron resonant tunneling transistor

metal gate

resonant tunneling double barrier heterostructures

three dimensional resonant tunneling transistor

current-voltage characteristics

asymmetric gate

30 to 100 nm

W-GaAs

Publikations- och innehållstyp

kon (ämneskategori)

ref (ämneskategori)