Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays

• We propose a methodology and power models for an accuratehigh-level power estimation of physically partitionedand power-gated SRAM arrays. The models offer accurateestimation of both dynamic and leakage power, includingthe power dissipation due to emerging leakage mechanismssuch as gate oxide tunneling, for partitioned arrays that deploydata-retaining sleep techniques for leakage reduction.Using the proposed methodology, dynamic, leakage and totalpower of partitioned SRAM arrays can be estimated witha 97% accuracy in comparison to the power obtained byrunning full circuit-level simulations.

Ämnesord

NATURVETENSKAP  -- Data- och informationsvetenskap -- Datorteknik (hsv//swe)

NATURAL SCIENCES  -- Computer and Information Sciences -- Computer Engineering (hsv//eng)

Nyckelord

Deep Submicron

SRAM Power Modeling

VLSI

CMOS

Power Estimation

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