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Low-Power 400-Gbps ...
Low-Power 400-Gbps Soft-Decision LDPC FEC for Optical Transport Networks
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- Cushon, Kevin, 1982 (författare)
- Chalmers tekniska högskola,Chalmers University of Technology
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- Larsson-Edefors, Per, 1967 (författare)
- Chalmers tekniska högskola,Chalmers University of Technology
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- Andrekson, Peter, 1960 (författare)
- Chalmers tekniska högskola,Chalmers University of Technology
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(creator_code:org_t)
- 2016
- 2016
- Engelska.
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Ingår i: Journal of Lightwave Technology. - 0733-8724 .- 1558-2213. ; 34:18, s. 4304-4311
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Abstract
Ämnesord
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- We present forward error correction systems based on soft-decision low-density parity check (LDPC) codes for applications in 100–400-Gbps optical transport networks. These systems are based on the low-complexity “adaptive degeneration” decoding algorithm, which we introduce in this paper, along with randomly-structured LDPC codes with block lengths from 30 000 to 60 000 bits and overhead (OH) from 6.7% to 33%. We also construct a 3600-bit prototype LDPC code with 20% overhead, and experimentally show that it has no error floor above a bit error rate (BER) of 10−15 using a field-programmable gate array (FPGA)-based hardware emulator. The projected net coding gain at a BER of 10−15 ranges from 9.6 dB at 6.7% OH to 11.2 dB at 33% OH. We also present application-specific integrated circuit synthesis results for these decoders in 28 nm fully depleted silicon on insulator technology, which show that they are capable of 400-Gbps operation with energy consumption of under 3 pJ per information bit.
Ämnesord
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik -- Annan elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering -- Other Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Nyckelord
- Application-specific integrated circuit (ASIC) synthesis
- low-density parity-check (LDPC) codes
- low power
- forward error correction (FEC)
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