| 1. |
- Bezati, Endri, et al.
(författare)
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Clock-gating of streaming applications for energy efficient implementations on FPGAs
- 2016
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Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - 0278-0070. ; , s. 699-703
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Tidskriftsartikel (refereegranskat)abstract
- The paper investigates the reduction of dynamic power for streaming applications yielded by asynchronous dataflow designs by using clock gating techniques. Streaming applications constitute a very broad class of computing algorithms in areas such as signal processing, digital media coding, cryptography, video analytics, network routing and packet processing and many others. The paper introduces a set of techniques that, considering the dynamic streaming behavior of algorithms, can achieve power savings by selectively switching off parts of the circuits when they are temporarily inactive. The techniques being independent from the semantic of the application can be applied to any application and can be integrated into the synthesis stage of a high-level dataflow design flow. Experimental results of atsize applications synthesized on FPGAs platforms demonstrate power reductions achievable with no loss in data throughput.
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| 2. |
- Chang, Shuangshuang, et al.
(författare)
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Towards minimum WCRT bound for DAG tasks under prioritized list scheduling algorithms
- 2022
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Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - : IEEE. - 0278-0070 .- 1937-4151. ; 41:11, s. 3874-3885
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Tidskriftsartikel (refereegranskat)abstract
- Many modern real-time parallel applications can be modeled as a directed acyclic graph (DAG) task. Recent studies show that the worst-case response time (WCRT) bound of a DAG task can be significantly reduced when the execution order of the vertices is determined by the priority assigned to each vertex of the DAG. How to obtain the optimal vertex priority assignment, and how far from the best-known WCRT bound of a DAG task to the minimum WCRT bound are still open problems. In this paper, we aim to construct the optimal vertex priority assignment and derive the minimum WCRT bound for the DAG task. We encode the priority assignment problem into an integer linear programming (ILP) formulation. To solve the ILP model efficiently, we do not involve all variables or constraints. Instead, we solve the ILP model iteratively, i.e., we initially solve the ILP model with only a few primary variables and constraints, and then at each iteration, we increment the ILP model with the variables and constraints which are more likely to derive the optimal priority assignment. Experimental work shows that our method is capable of solving the ILP model optimally without involving too many variables or constraints, e.g., for instances with 50 vertices, we find the optimal priority assignment by involving 12.67% variables on average and within several minutes on average.
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| 3. |
- Chen, Gang, et al.
(författare)
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EDF-VD Scheduling of Flexible Mixed-Criticality System With Multiple-Shot Transitions
- 2018
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Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - 0278-0070 .- 1937-4151. ; 37:11, s. 2393-2403
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Tidskriftsartikel (refereegranskat)abstract
- The existing mixed-criticality (MC) real-time task models assume that once any high-criticality task overruns, all high-criticality jobs execute up to their most pessimistic WCET estimations simultaneously in a one-shot manner. This is very pessimistic in the sense of unnecessary resource overbooking. In this paper, we propose a more generalized mixed-critical real-time task model, called flexible MC model with multiple-shot transitions (FMC-MST), to address this problem. In FMC-MST, high-criticality tasks can transit multiple intermediate levels to handle less pessimistic overruns independently and to nonuni-formly scale the deadline on each level. We develop a run-time schedulability analysis for FMC-MST under EDF-VD scheduling, in which a better tradeoff between the penalties of low-criticality tasks and the overruns of high-criticality tasks is achieved to improve the service quality of low-criticality tasks. We also develop a resource optimization technique to find resource-efficient level-insertion configurations for FMC-MST task systems under MC timing constraints. Experiments demonstrate the effectiveness of FMC-MST compared with the state-of-the-art techniques.
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| 4. |
- Cui, L., et al.
(författare)
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A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash
- 2022
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Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 0278-0070 .- 1937-4151. ; 41:6, s. 1971-1975
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Tidskriftsartikel (refereegranskat)abstract
- For NAND flash memory, designing a good low-density parity-check (LDPC) decoding algorithm could ensure data reliability. When the decoding algorithm is implemented in hardware, it is necessary to achieve attractive trade off between implementation complexity and decoding performance. In this paper, a novel low bit-width decoding scheme is introduced. In this scheme, the Quasi-Cyclic LDPC (QC-LDPC) is used, and the row-layered normalized min-sum algorithm is improved by restricting the amplitude of minimum and second-minimum values in each check node (CN) updating. The simulation shows that our approach achieves a lower UBER (Uncorrectable Bit Error Rate) with a negligible increase in computational complexity, especially with low precision input log-likelihood ratio (LLR).
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| 5. |
- Dai, Gaoyang, et al.
(författare)
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Response-Time Analysis of Limited-Preemptive Sporadic DAG Tasks
- 2022
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Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 0278-0070 .- 1937-4151. ; 41:11, s. 3673-3684
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Tidskriftsartikel (refereegranskat)abstract
- Guaranteeing timing constraints for parallel real-time applications deployed on multicore platforms is challenging, especially for applications containing non-preemptive execution blocks, that suffer from priority inversions. In this article, we propose to model such applications using a sporadic directed acyclic graph (DAG) model where preemption may take place only between the nodes of a DAG task. We present a new method for response-time analysis of such tasks scheduled with the global fixed-priority scheduling policy. We show that our method outperforms the state-of-the-art techniques significantly in terms of resource utilization in experimental evaluations using both benchmark and randomly generated task sets. We also present a method to deal with global EDF scheduling, which is a new technique proposed for response time analysis of sporadic DAG tasks with non-preemptive nodes.
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| 6. |
- Daneshtalab, M., et al.
(författare)
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Memory-Efficient On-Chip Network With Adaptive Interfaces
- 2012
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Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 0278-0070 .- 1937-4151. ; 31:1, s. 146-159
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Tidskriftsartikel (refereegranskat)abstract
- To achieve higher memory bandwidth in network-based multiprocessor architectures, multiple dynamic random access memories can be accessed simultaneously. In such architectures, not only resource utilization and latency are the critical issues but also a reordering mechanism is required to deliver the response transactions of concurrent memory accesses in-order. In this paper, we present a memory-efficient on-chip network architecture to cope with these issues efficiently. Each node of the network is equipped with a novel network interface (NI) to deal with out-of-order delivery, and a priority-based router to decrease the network latency. The proposed NI exploits a streamlined reordering mechanism to handle the in-order delivery and utilizes the advance extensible interface transaction-based protocol to maintain compatibility with existing intellectual property cores. To improve the memory utilization and reduce the memory latency, an optimized memory controller is integrated in the presented NI. Experimental results with synthetic test cases demonstrate that the proposed on-chip network architecture provides significant improvements in average network latency (16%), average memory access latency (19%), and average memory utilization (22%).
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| 7. |
- Ejlali, Alireza, et al.
(författare)
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Low-Energy Standby-Sparing for Hard Real-Time Systems
- 2012
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Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 0278-0070 .- 1937-4151. ; 31:3, s. 329-342
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Tidskriftsartikel (refereegranskat)abstract
- Time-redundancy techniques are commonly used in real-time systems to achieve fault tolerance without incurring high energy overhead. However, reliability requirements of hard real-time systems that are used in safety-critical applications are so stringent that time-redundancy techniques are sometimes unable to achieve them. Standby sparing as a hardware-redundancy technique can be used to meet high reliability requirements of safety-critical applications. However, conventional standby-sparing techniques are not suitable for low-energy hard real-time systems as they either impose considerable energy overheads or are not proper for hard timing constraints. In this paper we provide a technique to use standby sparing for hard real-time systems with limited energy budgets. The principal contribution of this paper is an online energy-management technique which is specifically developed for standby-sparing systems that are used in hard real-time applications. This technique operates at runtime and exploits dynamic slacks to reduce the energy consumption while guaranteeing hard deadlines. We compared the low-energy standby-sparing (LESS) system with a low-energy time-redundancy system (from a previous work). The results show that for relaxed time constraints, the LESS system is more reliable and provides about 26% energy saving as compared to the time-redundancy system. For tight deadlines when the time-redundancy system is not sufficiently reliable (for safety-critical application), the LESS system preserves its reliability but with about 49% more energy consumption.
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| 8. |
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| 9. |
- Feng, Zhiwei, et al.
(författare)
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On the scheduling of fault-tolerant time-sensitive networking with IEEE 802.1CB
- 2024
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Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 0278-0070 .- 1937-4151. ; 43:6, s. 1715-1728
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Tidskriftsartikel (refereegranskat)abstract
- Time-sensitive networking (TSN) has become the most popular technique in modern safety-critical automotive and industrial automation networks by providing deterministic transmission policies. However, the data of TSN messages may be affected by transient faults. IEEE 802.1CB, a reliability standard in TSN, protects against such faults by providing disjoint redundant routes for each stream. However, the unique assumption may present a new challenge, i.e., an inadequate number of redundant routes that may negatively impact stream scheduling. This article presents an offline fault-tolerant TSN scheduling approach that considers such impacts for real-time streams (such as time-trigger (TT) and audio video bridging (AVB) streams). Specifically, we intend to calculate the minimum upper bound number of disjoint routes required for each stream to meet the reliability requirements, subsequently enhancing the network's schedulability. We also propose a service degradation function for AVB streams when the network is under heavy load caused by redundant transmissions of TT streams. This function will maintain schedulability and reliability for AVB streams. Experiments with small- and large-scale synthetic networks show the efficiency.
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| 10. |
- Feng, Zhiwei, et al.
(författare)
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Online re-routing and re-scheduling of time-triggered flows for fault tolerance in time-sensitive networking
- 2022
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Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - : IEEE. - 0278-0070 .- 1937-4151. ; 41:11, s. 4253-4264
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Tidskriftsartikel (refereegranskat)abstract
- Time-Sensitive Networking (TSN) is an industry-standard networking protocol that is widely deployed in safety-critical industrial and automotive networks thanks to its advantages of deterministic transmission and bounded end-to-end delay for Time-Triggered (TT) flows. In this paper, we focus on TT flows, and address the issue of fault tolerance against permanent and transient faults with both spatial and temporal redundancy. We present an efficient heuristic algorithm for online incremental re-routing and re-scheduling of disrupted flows due to permanent faults, assuming the paths and schedules of existing flows stay fixed and cannot be modified. It is complementary to and can be combined with offline routing and scheduling algorithms for achieving fault tolerance based on Frame Replication and Elimination for Reliability (FRER) (IEEE 802.1CB). Performance evaluation shows that our approach can better recover the system's Degree of Redundancy (DoR) and has a higher acceptance rate than related work.
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