1. |
- Andreani, Pietro, et al.
(author)
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A 2.4-GHz CMOS monolithic VCO based on an MOS varactor
- 1999
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In: Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, 1999. ISCAS '99.. - 0780354710 ; 2, s. 557-560
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Conference paper (peer-reviewed)abstract
- A 2.4-GHz CMOS VCO is presented employing pMOS transistors as voltage-controlled capacitances and on-chip hollow spiral inductors. The design was implemented in a standard digital 0.8 μm CMOS process and exhibits a 15% tuning range at 2.5 V supply voltage and 9 mA supply current. Phase-noise measurements show a phase-noise of about -118 dBc/Hz at 1 MHz from the carrier
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2. |
- Andreani, Pietro, et al.
(author)
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A chip for linearization of RF power amplifiers using digital predistortion with a bit-parallel complex multiplier
- 1999
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In: Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, 1999. ISCAS '99.. - 0780354710 ; 1, s. 346-349
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Conference paper (peer-reviewed)abstract
- This paper presents a custom chip for linearization of RF power amplifiers using digital predistortion. The chip has been implemented in a standard digital 0.8 μm CMOS process with standard static cells and single-phase clocking. A systolic complex multiplier based on distributed arithmetic constitutes the core of the chip. The nonlinear function is realized with a look-up table containing complex gain factors applied to the complex multiplier. The maximum clock frequency was found by means of simulation to be 105 MHz corresponding to 21 Msamples/s throughput with 3 W power consumption using 5 V supply voltage. The fabricated chip is fully functional and has been measured up to 60 MHz clock frequency with 825 mW power consumption with 3.3 V supply voltage. Operation at 1.5 V supply voltage allows 10 MHz clock frequency with 35 mW power consumption
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3. |
- Johansson, Anders J, et al.
(author)
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Random Number Generation by Chaotic Double Scroll Oscillator on Chip
- 1999
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In: Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99.. - 0780354710 ; 5, s. 407-409
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Conference paper (peer-reviewed)abstract
- Generation of good non-repeatable and non-predictable random number sequences is of increasing importance, both in security applications and in simulations. A novel, compact system is presented in which a secure random number is generated by sampling a chaotic system and using this bitstream as the input to a pseudo-random generator. An optional hash function can be used on the seed in order to decrease the correlation. As all of the components can be implemented in a mixed-mode CMOS process, a totally self-contained non-repeatable random-number generator can be fabricated. This increases the security of the system, as very few of the systems parameters is observable from the outside. It also makes it possible to easily have available good random numbers in simulations if the chip is incorporated as a subsystem in an ordinary computer.
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4. |
- Meincke, Thomas, et al.
(author)
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Globally asynchronous locally synchronous architecture for large high-performance ASICs
- 1999
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In: ; 2, s. 512-515
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Conference paper (peer-reviewed)abstract
- Clock nets are the major source of power consumption in large, high-performance ASICs and a design bottleneck when it comes to tolerable clock skew. A way to obviate the global clock net is to partition the design into large synchronous blocks each having its own clock. Data with other blocks is exchanged asynchronously using handshake signals. Adopting such a strategy requires a methodology that supports: 1) a partitioning method dividing a design into the number of synchronous blocks such that the gain due to global clock net removal exceeds the communication overhead and 2) synthesis of handshake protocols to implement the data transfer between synchronous blocks. We describe this methodology and present results of applying it to a realistic design done in 0.25 micron, ranging in operating frequencies from 20 MHz to 1 GHz. The results show that the net power savings compared to fully synchronous designs are on an average about 30%
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5. |
- Vesterbacka, Mark, 1966-
(author)
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A robust differential scan flip-flop
- 1999
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In: Proc. 1999 IEEE Int. Symp. on Circuits and Systems, ISCAS'99. - 0780354710 ; , s. I-334-I-337
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Conference paper (peer-reviewed)abstract
- A flip-flop is proposed that is robust against smooth clock edges. This robustness simplifies the design of the clock net in large integrated circuits and lowers the power consumed in the clock driver compared to flip-flops needing sharper clock edges. The proposed flip-flop is realized using 20 MOSFETs and uses a single phase clock. It includes a multiplexer circuit at the input that is useful in a scan test. The flip-flop is semi-static in the sense that the master latch is static while the slave latch is dynamic. This allows the clock to be in the low state for an indefinitely long period, while the period of the high state is limited due to charge leakage. Therefore another circuit is also proposed that limits the pulse width of the clock. The use of this circuit enables design of a scan chain that can be clocked with an arbitrarily low frequency.
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