1. |
- Kuchcinski, Krzysztof, et al.
(author)
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Global approach to assignment and scheduling of complex behaviors based on HCDG and constraint programming
- 2003
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In: Journal of Systems Architecture. - 1383-7621. ; 49:12-15, s. 489-503
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Journal article (peer-reviewed)abstract
- This paper presents global high-level synthesis (HLS) approach which addresses the problem of synthesis of conditional behaviors under resource constraints. In proposed methodology, the conditional behaviors are represented by hierarchical conditional dependency graphs (HCDG) and synthesized using derived constraints programming (CP) models. Our synthesis methods exploit multicycle operations and chaining as well as conditional resource sharing and speculative execution at the same time. We assign both functional units and registers while making possible to conditionally share these components. These techniques are essential in HLS and the experiments carried out using the developed prototype system showed good performance of the synthesized designs and proved the feasibility of the presented approach. (C) 2003 Elsevier B.V. All rights reserved.
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2. |
- Cortes, Luis-Alejandro, et al.
(author)
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Modeling and formal verification of embedded systems based on a Petri net representation
- 2003
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In: Journal of systems architecture. - 1383-7621 .- 1873-6165. ; 49:12-15, s. 571-598
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Journal article (peer-reviewed)abstract
- In this paper we concentrate on aspects related to modeling and formal verification of embedded systems. First, we define a formal model of computation for embedded systems based on Petri nets that can capture important features of such systems and allows their representation at different levels of granularity. Our modeling formalism has a well-defined semantics so that it supports a precise representation of the system, the use of formal methods to verify its correctness, and the automation of different tasks along the design process. Second, we propose an approach to the problem of formal verification of embedded systems represented in our modeling formalism. We make use of model checking to prove whether certain properties, expressed as temporal logic formulas, hold with respect to the system model. We introduce a systematic procedure to translate our model into timed automata so that it is possible to use available model checking tools. We propose two strategies for improving the verification efficiency, the first by applying correctness-preserving transformations and the second by exploring the degree of parallelism characteristic to the system. Some examples, including a realistic industrial case, demonstrate the efficiency of our approach on practical applications. © 2003 Elsevier B.V. All rights reserved.
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3. |
- Vlassov, Vladimir, et al.
(author)
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Analytical modeling of multithreaded architectures
- 2000
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In: Journal of systems architecture. - 1383-7621 .- 1873-6165. ; 46:13, s. 1205-1230
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Journal article (peer-reviewed)abstract
- Multithreading is used for hiding long memory latency in uniprocessors and multiprocessor computer systems and aims at increasing system efficiency. In such an architecture, a number of threads are allocated to each processing element (PE) and whenever a running thread becomes suspended the PE switches to another ready thread. In this paper, we discuss analytical modeling of coarsely multithreaded architectures and present two analytical models: (i) a deterministic model, where the timing parameters (e.g., context switching time, threads's run length, and memory latency) are assumed to be constant, and (ii) a stochastic model where the timing parameters are random variables. Both models provide a framework to study the dependence of the MTA efficiency on design parameters of the target architecture and its workload. The deterministic model, as well as asymptotic bounding analysis of the stochastic model, allows to determine upper bounds and some break points of the MTA efficiency such as stability (saturation) points, whereas the stochastic model provides more accurate prediction of the efficiency.
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4. |
- Öberg, Johnny, et al.
(author)
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Grammar-based design of embedded systems
- 2001
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In: Journal of systems architecture. - : Elsevier. - 1383-7621 .- 1873-6165. ; 47:3-4, s. 225-240
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Journal article (peer-reviewed)abstract
- Grammars define syntax of languages and as such have not been commonly considered as methods for design, despite well-known applications in computer science. Only in recent years grammar-based design has become a promising research field and the first commercial tools have appeared on the market. This paper reviews the basic concepts of applying grammars to electronic design - in particular to the device driver synthesis of communication protocols for embedded software, to the design of custom-hardware, and to the virtual prototyping of DSP systems. The paper shows the power of these methods, presents the latest research results and discusses future developments in this field.
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5. |
- Ahmed, Saad, et al.
(author)
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A survey on program-state retention for transiently-powered systems
- 2021
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In: Journal of systems architecture. - : Elsevier B.V.. - 1383-7621 .- 1873-6165. ; 115
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Journal article (peer-reviewed)abstract
- Low-power small-scale embedded sensing systems employing batteries generally impose high maintenance costs. To enable maintenance-free operation, they are powered from energy harvested from the environment thus making them batteryless. However, due to high variance of ambient energy, these batteryless embedded devices are unable to harvest enough energy from the environment required for continuous device operation thus hampering application progress and causing frequent loss of volatile program-state. Therefore, these batteryless devices have to employ state retention mechanisms to save the volatile program-state to non-volatile storage before interruption. These batteryless embedded sensing devices are known as transiently-powered systems (TPS). In this article, we survey existing literature to identify strategies and techniques used by each existing literature to decide what amount of volatile program-state needs to be saved and when to save it. We list the challenges in retaining program-state across periods of energy unavailability and how existing state-of-the-art solutions tackle them. We also describe different memory models and discuss factors governing the choice of each model for TPS deployment.
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6. |
- Ashjaei, Mohammad, et al.
(author)
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MTU Configuration for Real-Time Switched Ethernet Networks
- 2016
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In: Journal of systems architecture. - : Elsevier BV. - 1383-7621 .- 1873-6165. ; 70, s. 15-25
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Journal article (peer-reviewed)abstract
- In this paper, we show that in real-time switched Ethernet networks reducing the Maximum Transmission Unit (MTU) size may cause an increase or decrease in the response time of messages. This contradicting behavior arises an optimization problem for configuring the MTU size. We formulate the optimization problem in the context of the multi-hop HaRTES architecture, which is a hard real-time Ethernet protocol. As part of the solution, we propose a search-based algorithm to achieve optimum solutions. We modify the algorithm by presenting two techniques to reduce the search space. Then, we propose a heuristic algorithm with a pseudo-polynomial time complexity based on the search-based algorithm. We perform several experiments, and we show that the proposed heuristic results in an improvement regarding messages response times, compared with configuring the MTU to the maximum or minimum values. Moreover, we show in small network configurations that the heuristic performs as good as the search-based algorithm in many cases.
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7. |
- Ashjaei, Mohammad, et al.
(author)
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SEtSim : A modular simulation tool for switched Ethernet networks
- 2016
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In: Journal of systems architecture. - : Elsevier BV. - 1383-7621 .- 1873-6165. ; 65, s. 1-14
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Journal article (peer-reviewed)abstract
- Using high bandwidth network technologies in real-time applications, for example in automotive systems, is rapidly increasing. In this context, switched Ethernet-based protocols are becoming more popular due to their features such as providing a collision-free domain for transmission of messages. Moreover, switched Ethernet is a mature technology. Several protocols based on switched Ethernet have been proposed over the years, tuned for time critical applications. However, research for improving the features and performance of these protocols is still on-going. In order to evaluate the performance of early stage proposed protocols, the mathematical analysis and/or experiments are required. However, performing an experiment for complex network topologies with a large set of messages is not effortless. Therefore, using a simulation based approach for evaluating a protocol's performance and/or properties is highly useful. As a response to this we have developed a simulator, called SEtSim, for switched Ethernet networks. SEtSim is developed based on Simulink, and it currently supports different network topologies of the FIT-SE protocol as well as Ethernet AVB protocol. However, the kernel of SEtSim is designed such that it is possible to add and integrate other switched Ethernet-based protocols. In this paper, we describe the design of SEtSim and we show its scalability.
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8. |
- Ashjaei, Seyed Mohammad Hossein, 1980-, et al.
(author)
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A novel frame preemption model in TSN networks
- 2021
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In: Journal of systems architecture. - : Elsevier B.V.. - 1383-7621 .- 1873-6165. ; 116
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Journal article (peer-reviewed)abstract
- This paper identifies a limitation in the frame preemption model in the TSN standard (IEEE 802.1Q-2018), due to which high priority frames can experience significantly long blocking delays, thereby exacerbating their worst-case response times. This limitation can have a considerable impact on the design, analysis and performance of TSN-based systems. To address this limitation, the paper presents a novel and more efficient frame preemption model in the TSN standard that allows over 90% reduction in the maximum blocking delay leading to lower worst-case response times of high priority frames compared to the frame preemption model used in the existing works. The paper also shows that the improvement becomes even more significant in multi-switch TSN networks. In order to evaluate the effects of preemption, the paper performs simulations by enabling and disabling preemptions as well as enabling and disabling the Hold/Release mechanism supported by TSN. Furthermore, the paper performs a comparative evaluation of the two models of frame preemption in TSN using simulations. The evaluation shows that the maximum response times of high priority frames can be significantly reduced with very small impact on the response times of lower priority frames. The paper also shows the improvement in the maximum response times of higher priority frames using an automotive industrial use case that employs a multi-hop TSN network for on-board communication.
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9. |
- Ashjaei, Seyed Mohammad Hossein, 1980-, et al.
(author)
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Time-Sensitive Networking in automotive embedded systems : State of the art and research opportunities
- 2021
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In: Journal of systems architecture. - : Elsevier B.V.. - 1383-7621 .- 1873-6165. ; 117
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Journal article (peer-reviewed)abstract
- The functionality advancements and novel customer features that are currently found in modern automotive systems require high-bandwidth and low-latency in-vehicle communications, which become even more compelling for autonomous vehicles. In a recent effort to meet these requirements, the IEEE Time-Sensitive Networking (TSN) task group has developed a set of standards that introduce novel features in Switched Ethernet. TSN standards offer, for example, a common notion of time through accurate and reliable clock synchronization, delay bounds for real-time traffic, time-driven transmissions, improved reliability, and much more. In order to fully utilize the potential of these novel protocols in the automotive domain, TSN should be seamlessly integrated into the state-of-the-art and state-of-practice model-based development processes for automotive embedded systems. Some of the core phases in these processes include software architecture modeling, timing predictability verification, simulation, and hardware realization and deployment. Moreover, throughout the development of automotive embedded systems, the safety and security requirements specified on these systems need to be duly taken into account. In this context, this work provides an overview of TSN in automotive applications and discusses the recent technological developments relevant to the adoption of TSN in automotive embedded systems. The work also points at the open challenges and future research directions.
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10. |
- Bakhshi, Zeinab, 1986-, et al.
(author)
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Analyzing the performance of persistent storage for fault-tolerant stateful fog applications
- 2023
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In: Journal of systems architecture. - 1383-7621 .- 1873-6165. ; 144
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Journal article (peer-reviewed)abstract
- In this paper, we analyze the scalability and performance of a persistent, fault-tolerant storage approach that provides data availability and consistency in a distributed container-based architecture with intended use in industrial control applications. We use simulation to evaluate the performance of this storage system in terms of scalability and failures. As the industrial applications considered have timing constraints, the simulation results show that for certain failure patterns, it is possible to determine whether the storage solution can meet critical deadlines. The presented approach is applicable for evaluating timing constraints also of other container-based critical applications that require persistent storage.
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