| 1. |
- Aminifar, Amir, et al.
(author)
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Control-Quality Driven Design of Cyber-Physical Systems with Robustness Guarantees
- 2013
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In: Design, Automation & Test in Europe (DATE 2013). - : IEEE. - 1530-1591. - 9781467350716 ; , s. 1093-1098
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Conference paper (peer-reviewed)abstract
- Many cyber-physical systems comprise several control applications sharing communication and computation resources. The design of such systems requires special attention due to the complex timing behavior that can lead to poor control quality or even instability. The two main requirements of control applications are: (1) robustness and, in particular, stability and (2) high control quality. Although it is essential to guarantee stability and provide a certain degree of robustness even in the worst-case scenario, a design procedure which merely takes the worst-case scenario into consideration can lead to a poor expected (average-case) control quality, since the design is solely tuned to a scenario that occurs very rarely. On the other hand, considering only the expected quality of control does not necessarily provide robustness and stability in the worst-case. Therefore, both the robustness and the expected control quality should be taken into account in the design process. This paper presents an efficient and integrated approach for designing high-quality cyber-physical systems with robustness guarantees.
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| 2. |
- Abdulla, Parosh Aziz, et al.
(author)
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Verifying Safety and Liveness for the FlexTM Hybrid Transactional Memory
- 2013
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In: <em>Design, Automation & Test in Europe (DATE 2013), Grenoble, France, March 18-22, 2013.</em>. - Grenoble, France : IEEE. - 9781467350716 ; , s. 785-790
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Conference paper (peer-reviewed)abstract
- We consider the verification of safety (strict se- rializability and abort consistency) and liveness (obstruction and livelock freedom) for the hybrid transactional memory framework FLEXTM. This framework allows for flexible imple- mentations of transactional memories based on an adaptation of the MESI coherence protocol. FLEXTM allows for both eager and lazy conflict resolution strategies. Like in the case of Software Transactional Memories, the verification problem is not trivial as the number of concurrent transactions, their size, and the number of accessed shared variables cannot be a priori bounded. This complexity is exacerbated by aspects that are specific to hardware and hybrid transactional memories. Our work takes into account intricate behaviours such as cache line based conflict detection, false sharing, invisible reads or non-transactional instructions. We carry out the first automatic verification of a hybrid transactional memory and establish, by adopting a small model approach, challenging properties such as strict serializability, abort consistency, and obstruction freedom for both an eager and a lazy conflict resolution strategies. We also detect an example that refutes livelock freedom. To achieve this, our prototype tool makes use the latest antichain based techniques to handle systems with tens of thousands of states.
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| 3. |
- Aminifar, Amir, et al.
(author)
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Bandwidth-Efficient Controller-Server Co-Design with Stability Guarantees
- 2014
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In: [Host publication title missing]. - 1530-1591.
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Conference paper (peer-reviewed)abstract
- Many cyber-physical systems comprise several control applications implemented on a shared platform, for which stability is a fundamental requirement. This is as opposed to the classical hard real-time systems where often the criterion is meeting the deadline. The stability of control applications depends on not only the delay experienced, but also the jitter. Therefore, the notion of deadline is considered to be artificial for control applications which promotes the need for new techniques for designing cyber-physical systems. The approach in this paper is built on a server-based resource reservation mechanism, which provides compositionality, isolation, and the opportunity of systematic controller–server co-design. We address the controller–server co-design of such systems to obtain design solutions with the minimal bandwidth to guarantee stability.
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| 4. |
- Attarzadeh Niaki, Seyed Hosein, 1984-, et al.
(author)
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An Automated Parallel Simulation Flow for Heterogeneous Embedded Systems
- 2013
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In: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013. - 9781467350716 ; , s. 27-30
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Conference paper (peer-reviewed)abstract
- Simulation of complex embedded and cyber-physical systems requires exploitation of the computation power ofavailable parallel architectures. Current simulation environments either do not address this parallelism or use separate models for parallel simulation and for analysis and synthesis, which might lead to model mismatches. We extend a formal modeling framework targeting heterogeneous systems with elements that enable parallel simulations. An automated flow is then proposed that starting from a serial executable specification generates an efficient MPI-based parallel simulation model by using aconstraint-based method. The proposed flow generates parallel models with acceptable speedups for a representative example.
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| 5. |
- Bardizbanyan, Alen, 1986, et al.
(author)
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Reducing set-associative L1 data cache energy by early load data dependence detection (ELD3)
- 2014
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In: Proceedings -Design, Automation and Test in Europe, DATE. - 1530-1591. - 9783981537024
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Conference paper (peer-reviewed)abstract
- Fast set-associative level-one data caches (L1 DCs) access all ways in parallel during load operations for reduced access latency. This is required in order to resolve data dependencies as early as possible in the pipeline, which otherwise would suffer from stall cycles. A significant amount of energy is wasted due to this fast access, since the data can only reside in one of the ways. While it is possible to reduce L1 DC energy usage by accessing the tag and data memories sequentially, hence activating only one data way on a tag match, this approach significantly increases execution time due to an increased number of stall cycles. We propose an early load data dependency detection (ELD 3) technique for in-order pipelines. This technique makes it possible to detect if a load instruction has a data dependency with a subsequent instruction. If there is no such dependency, then the tag and data accesses for the load are sequentially performed so that only the data way in which the data resides is accessed. If there is a dependency, then the tag and data arrays are accessed in parallel to avoid introducing additional stall cycles. For the MiBench benchmark suite, the ELD3 technique enables about 49% of all load operations to access the L1 DC sequentially. Based on 65-nm data using commercial SRAM blocks, the proposed technique reduces L1 DC energy by 13%.
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| 6. |
- Buttazzo, Giorgio C., et al.
(author)
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Rate-Adaptive Tasks: Model, Analysis, and Design Issues
- 2014
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In: [Host publication title missing]. - 1530-1591.
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Conference paper (peer-reviewed)abstract
- In automotive systems, some of the engine control tasks are triggered by specific crankshaft rotation angles and are designed to adapt their functionality based on the angular velocity of the engine. This paper proposes a new task model for specifying such a type of real-time activities and presents an approach for analyzing the system feasibility under dynamic scheduling for different scenarios. A design method is also discussed to determine the most suitable switching speeds for adapting the functionality of tasks without exceeding a desired utilization. Finally, a number of research directions are highlighted to extend the current results to more complex and realistic scenarios.
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| 7. |
- Griessl, R., et al.
(author)
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Evaluation of heterogeneous AIoT Accelerators within VEDLIoT
- 2023
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In: Proceedings -Design, Automation and Test in Europe, DATE. - 1530-1591. ; 2023-April
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Conference paper (peer-reviewed)abstract
- Within VEDLIoT, a project targeting the development of energy-efficient Deep Learning for distributed AIoT applications, several accelerator platforms based on technologies like CPUs, embedded GPUs, FPGAs, or specialized ASICs are evaluated. The VEDLIoT approach is based on modular and scalable cognitive IoT hardware platforms. Modular microserver technology enables the integration of different, heterogeneous accelerators into one platform. Benchmarking of the different accelerators takes into account performance, energy efficiency and accuracy. The results in this paper provide a solid overview regarding available accelerator solutions and provide guidance for hardware selection for AIoT applications from far edge to cloud. VEDLIoT is an H2020 EU project which started in November 2020. It is currently in an intermediate stage. The focus is on the considerations of the performance and energy efficiency of hardware accelerators. Apart from the hardware and accelerator focus presented in this paper, the project also covers toolchain, security and safety aspects. The resulting technology is tested on a wide range of AIoT applications.
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| 8. |
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| 9. |
- Jiang, Ke, et al.
(author)
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Optimization of Secure Embedded Systems with Dynamic Task Sets
- 2013
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In: Design, Automation & Test in Europe (DATE 2013). - : IEEE. - 9781467350716 ; , s. 1765-1770
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Conference paper (peer-reviewed)abstract
- In this paper, we approach embedded systems design from a new angle that considers not only quality of service but also security as part of the design process. Moreover, we also take into consideration the dynamic aspect of modern embedded systems in which the number and nature of active tasks are variable during run-time. In this context, providing both high quality of service and guaranteeing the required level of security becomes a difficult problem. Therefore, we propose a novel secure embedded systems design framework that efficiently solves the problem of run-time quality optimization with security constraints. Experiments demonstrate the efficiency of our proposed techniques.
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| 10. |
- Lifa, Adrian Alin, et al.
(author)
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Dynamic Configuration Prefetching Based on Piecewise Linear Prediction
- 2013
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In: Design, Automation & Test in Europe (DATE 2013). - : IEEE. - 9781467350716 ; , s. 815-820
-
Conference paper (peer-reviewed)abstract
- Modern systems demand high performance, as well as high degrees of flexibility and adaptability. Many current applications exhibit a dynamic and nonstationary behavior, having certain characteristics in one phase of their execution, that will change as the applications enter new phases, in a manner unpredictable at design-time. In order to meet the performance requirements of such systems, it is important to have on-line optimization algorithms, coupled with adaptive hardware platforms, that together can adjust to the run-time conditions. We propose an optimization technique that minimizes the expected execution time of an application by dynamically scheduling hardware prefetches. We use a piecewise linear predictor in order to capture correlations and predict the hardware modules to be reached. Experiments show that the proposed algorithm outperforms the previous state-of-art in reducing the expected execution time by up to 27% on average.
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