| 1. |
- Amirmazlaghani, Mina, 1984, et al.
(författare)
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Feasibility of Room-Temperature GHz-THz Direct Detection in Graphene Through Hot-Carrier Effect
- 2018
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Ingår i: IEEE Transactions on Device and Materials Reliability. - 1530-4388 .- 1558-2574. ; 18:3, s. 429-437
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Tidskriftsartikel (refereegranskat)abstract
- Recent theories suggest that the photo thermoelectric effect dominates the photo response in graphene. Hot-carrier generation arising from carrier multiplication in graphene under the incident light is introduced as the main cause of this effect. Here, we investigate the possibility of GHz-THz direct detection in a graphene-based device through Hot-carrier effect. The proposed structure is a Schottky junction between graphene and Si. We have measured the optical properties of the junction under 86 GHz and 0.102 THz radiations at room temperature. We have repeated the experiments at cryogenic temperatures down to 150 K. The minimum responsivity of the junction is measured as 2x10(4) V/W under 0.102 THz radiations at room temperature. This value increases five-fold at the cryogenic temperatures. We discuss the physics behind room temperature operation of the device based on the photo thermoelectric effect and the hot-carrier generation in graphene under the illuminations. Room temperature and direct detection of GHz and THz radiation in the graphene-Si junction can be practical evidence of hot-carrier generation in graphene under the incident illuminations.
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| 2. |
- Axelsson, Olle, 1986, et al.
(författare)
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The Effect of Forward Gate Bias Stress on the Noise Performance of Mesa Isolated GaN HEMTs
- 2015
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Ingår i: IEEE Transactions on Device and Materials Reliability. - : Institute of Electrical and Electronics Engineers (IEEE). - 1530-4388 .- 1558-2574. ; 15:1, s. 40-46
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Tidskriftsartikel (refereegranskat)abstract
- This study investigates degradation of gallium nitride (GaN) high-electron mobility transistor (HEMT) noise performance after both dc and RF stress with forward gate current. The results are used to facilitate optimization of the robustness of GaN low-noise amplifiers (LNAs). It is shown that forward biasing the gate of a GaN HEMT results in permanent degradation of noise performance and gate current leakage, without affecting S-parameters and drain current characteristics. The limit of safe operation of the 2 x 50 mu m devices in this study is found to be between 10 and 20 mW dissipated in the gate diode for both dc and RF stress. We propose that degradation could be caused by excessive leakage through the mesa sidewalls at the edges of each gate finger. Circuit simulations may be used together with device robustness rating to optimize LNAs for maximum input power tolerance. Using a resistance in the gate biasing network of 10 k Omega, it is estimated that an LNA utilizing a 2 x 50 mu m device could withstand input power levels up to 33 dBm without degradation in noise performance.
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| 3. |
- Fagerlind, Martin, et al.
(författare)
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Influence of Large-Aspect-Ratio Surface Roughness on Electrical Characteristics of AlGaN/AlN/GaN HFETs
- 2012
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Ingår i: IEEE transactions on device and materials reliability. - : Institute of Electrical and Electronics Engineers (IEEE). - 1530-4388 .- 1558-2574. ; 12:3, s. 538-546
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Tidskriftsartikel (refereegranskat)abstract
- The effect of large-aspect-ratio surface roughness of AlGaN/GaN wafers is investigated. The roughness has a surface morphology consisting of hexagonal peaks with maximum peak-to-valley height of more than 100 nm and lateral peak-to-peak distance between 25 and 100 mu m. Two epitaxial wafers grown at the same time on SiC substrates having different surface orientation and with a resulting difference in AlGaN surface roughness are investigated. Almost no difference is seen in the electrical characteristics of the materials, and the electrical uniformity of the rough material is comparable to that of the smoother material. The reliability of heterostructure field-effect transistors from both materials have been tested by stressing devices for up to 100 h without any significant degradation. No critical effect, from the surface roughness, on device fabrication is experienced, with the exception that the roughness will directly interfere with step-height measurements.
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| 4. |
- Fagerlind, Martin, 1980, et al.
(författare)
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Influence of Large-Aspect-Ratio Surface Roughness on Electrical Characteristics of AlGaN/AlN/GaN HFETs
- 2012
-
Ingår i: IEEE Transactions on Device and Materials Reliability. - : Institute of Electrical and Electronics Engineers (IEEE). - 1530-4388 .- 1558-2574. ; 12:3, s. 538-546
-
Tidskriftsartikel (refereegranskat)abstract
- The effect of large-aspect-ratio surface roughness of AlGaN/GaN wafers is investigated. The roughness has a surface morphology consisting of hexagonal peaks with maximum peak-to-valley height of more than 100 nm and lateral peak-to-peak distance between 25 and 100 mu m. Two epitaxial wafers grown at the same time on SiC substrates having different surface orientation and with a resulting difference in AlGaN surface roughness are investigated. Almost no difference is seen in the electrical characteristics of the materials, and the electrical uniformity of the rough material is comparable to that of the smoother material. The reliability of heterostructure field-effect transistors from both materials have been tested by stressing devices for up to 100 h without any significant degradation. No critical effect, from the surface roughness, on device fabrication is experienced, with the exception that the roughness will directly interfere with step-height measurements.
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| 5. |
- Lotfi, Sara, et al.
(författare)
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Investigating reliability and stress mechanisms of DC and large-signal stressed CMOS 65-nm RF-LDMOS by gate current characterization
- 2015
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Ingår i: IEEE transactions on device and materials reliability. - 1530-4388 .- 1558-2574. ; 15:2, s. 191-197
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents reliability measurements under DC and large-signal conditions of an LDMOS transistor integrated in a 65 nm CMOS process. The gate current was measured with high resolution across the whole operation area with an atto-sense unit, and distinct behavior was seen in the gate current characteristics due to hot-carrier injection (HCI) and Fowler-Nordheim (FN) tunneling. Several bias points were chosen for DC stress of the transistor and degradation of important parameters in terms of RF operation were studied. Furthermore, the behavior from DC stress was compared to large-signal stress of the device in class AB where output power was monitored. Results show that operation at a supply voltage of 3.3 V shows no significant drift of transistor parameters while operation at 5 V shows increase in on-resistance but no changes in quiescent current or threshold voltage. These results are in coherence with what DC stress at quiescent bias points for class AB showed and may imply that DC stress measurements are sufficient in order to understand transistor reliability during RF operation.
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| 6. |
- Reviriego, Pedro, et al.
(författare)
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Number of Events and Time to Failure Distributions for Error Correction Protected Memories
- 2010
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Ingår i: IEEE transactions on device and materials reliability. - 1530-4388 .- 1558-2574. ; 10:3, s. 381-389
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Tidskriftsartikel (refereegranskat)abstract
- Designing the memory system for an application has always been a complex task. This complexity has been increasing in the last years due the technology scaling, since memories are becoming more sensitive to soft errors. This issue is aggravated when the application is running in a harsh environment, e. g., in the presence of intense radiation sources. Therefore, the task to determine the optimal memory size and optimal protection mechanism is a challenge for designers to provide appropriate fault tolerance. In this paper, some classical reliability parameters, as the mean time to failure and the mean number of events to failure are revisited, but extending their scope with their probabilistic distributions. These can be of great help to designers when analyzing the consequences on reliability of certain decisions related to the memory size and protection codes.
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| 7. |
- Zanotti, Tommaso, et al.
(författare)
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Guidelines for the Design of Random Telegraph Noise-Based True Random Number Generators
- 2024
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Ingår i: IEEE Transactions on Device and Materials Reliability. - 1530-4388 .- 1558-2574. ; 24:2, s. 184-193
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Tidskriftsartikel (refereegranskat)abstract
- The development of a robust and secure hardware for the Internet of Things (IoT) and edge computing requires improvements in the existing low-power and low-cost hardware security primitives. Among the various available technologies, true random number generators (TRNGs) that leverage random telegraph noise (RTN) from nanoelectronics devices have emerged as effective solutions. However, the temporal instabilities in the RTN signal, such as the DC drift and temporary inhibition, are a few of the key reliability challenges for the TRNG circuits. In this study, we have utilized experimental RTN data collected from the commonly used gate dielectrics, including silicon dioxide (SiO2), hafnium dioxide (HfO2), and 2D crystalline hexagonal boron nitride (h-BN) to identify the crucial reliability challenges for RTN-based TRNG circuits. We have analyzed the impact of RTN instabilities and of circuit parameters on the output randomness and propose reliability aware design guidelines. Finally, we design and simulate an RTN-based TRNG circuit using a 130 nm CMOS technology and evaluate its reliability at the circuit level.
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| 8. |
- Åkerman, Johan, et al.
(författare)
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Demonstrated reliability of 4-Mb MRAM
- 2004
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Ingår i: IEEE transactions on device and materials reliability. - 1530-4388 .- 1558-2574. ; 4:3, s. 428-435
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Tidskriftsartikel (refereegranskat)abstract
- The successful commercialization of MRAM will rely on providing customers with a robust and reliable memory product. The intrinsic reliability of magnetoresistive tunnel junction (MTJ) memory bits and the metal interconnect system of MRAM are two areas of great interest due to the new materials involved in this emerging technology. Time dependent dielectric breakdown (TDDB) and resistance drift were the two main failure mechanisms identified for intrinsic memory bit reliability. Results indicated that a lifetime over 10 years is achievable under the operating condition. For metal interconnect system, the initial results of Cu with magnetic cladding have met the reliability performance of typical nonclad Cu backend process in electromigration (EM) and iso-thermal annealing (ITA). Finally data retention is demonstrated over times orders of magnitude longer than 10 years.
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| 9. |
- Roll, Guntrade, et al.
(författare)
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Effect of Gate Voltage Stress on InGaAs MOSFET with HfO2 or Al2O3 Dielectric
- 2016
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Ingår i: IEEE Transactions on Device and Materials Reliability. - 1530-4388. ; 16:2, s. 112-116
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Tidskriftsartikel (refereegranskat)abstract
- InGaAs nMOSFETs with Al2O3 and HfO2 as dielectric are analyzed. The devices with Al 2O3 show a slightly better subthreshold slope. Both high-κ's have an equal transconductance frequency dispersion (gm-f). A reduction of gm-f is reached by scaling the HfO2 thickness. Positive gate stress leads to an increase in threshold voltage and subthreshold slope for all oxides. DC-gmax degradation is related purely to creation or activation of additional border traps during stress. The RF-gmax is not degraded. Similar time constants hint to a relation between the (semi-)stable degradation of DC-gmax and the threshold voltage increase. For the samples with HfO2, the effects of gate-stress induced additional border traps can only be detected at low frequencies. The created or activated defects are most likely located deep in the oxide. For Al2O3, the effect of additional border traps is also measurable at higher frequencies. The defects are created both closer to the Al2O3/InGaAs interface and deeper in the oxide.
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