| 1. |
- Ashjaei, Seyed Mohammad Hossein, 1980-, et al.
(author)
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Implications of Various Preemption Configurations in TSN Networks
- 2022
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In: IEEE Embedded Systems Letters. - 1943-0663 .- 1943-0671. ; 14:1, s. 39-42
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Journal article (peer-reviewed)abstract
- Time Sensitive Networking (TSN) is a set of standards developed by the IEEE 802.1 task group to support high-bandwidth and low latency predictable network communication. Configuration of TSN networks is a daunting task as there are several novel features in TSN and numerous possibilities can arise by considering combinations of these features. This letter investigates the impact of various unexplored frame-preemption configurations in TSN networks on the timing behaviours of various traffic classes. These configurations correspond to different combinations of settings in TSN with respect to the credit-based shaper, time-aware shaper, Hold & Release mechanism and frame preemption. The letter provides evaluation of these configurations by means of an analytical discussion and simulation experiments. The results and implications discussed in this letter can serve as useful guidelines for the network designers when configuring TSN networks with regards to the addressed features.
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| 2. |
- Anagnostopoulos, Iraklis, et al.
(author)
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Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations
- 2011
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In: IEEE Embedded Systems Letters. - 1943-0663. ; 3:2, s. 66-69
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Journal article (peer-reviewed)abstract
- Multiprocessor system-on-chip (MPSoCs) have attracted significant attention since they are recognized as a scalable paradigm to interconnect and organize a high number of cores. Current multicore embedded systems exhibit increased levels of dynamicbehavior, leading to unexpected memory footprint variations unknown at design time.Dynamic memory management (DMM) is a promising solution for such types of dynamicsystems. Although some efficient dynamic memory managers have been proposed for conventional bus-based MPSoC platforms, there are no DMM solutions regarding the constraints and the opportunities delivered by the physical distribution of multiple memorynodes of the platform. In this work, we address the problem of providing customizedmicrocoded DMM on MPSoC platforms with distributed memory organization. Customization is enabled at application-and platform-level. Results show that customizedmicrocoded DMM can serve approximately 7× more allocation requests compared to puredistributed memory platforms and perform 25% faster than the corresponding high-level implementation in C language.
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| 3. |
- Asplund, Fredrik, 1977-, et al.
(author)
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Rapid Integration of CPS Security and Safety
- 2018
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In: IEEE Embedded Systems Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 1943-0663.
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Journal article (peer-reviewed)abstract
- The security and safety of Cyber-Physical Systems (CPS) often influence each other. Ensuring that this does not have negative implications might require a large and rigorous effort during the development of CPS. However, early in the lifecycle, quick feedback can be valuable helping security and safety engineers to understand how seemingly trivial design choices in their domain may have unacceptable implications in the other.We propose the Cyber Risk Assessment Framework (CRAF) for this purpose. The CRAF is based on openly available and widely used taxonomies from the safety and security domains, and a unique mapping of where loss of data security may impact aspects of data with safety implications. This paper represents the first time these different elements have been brought together into a single framework with an associated process. Through examples from within our organisations we show how this framework can be put to good use.
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| 4. |
- Huang, L. -T, et al.
(author)
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WeNA : Deterministic Run-time Task Mapping for Performance Improvement in Many-core Embedded Systems
- 2015
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In: IEEE Embedded Systems Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 1943-0663. ; 7:4, s. 93-96
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Journal article (peer-reviewed)abstract
- Many-core embedded systems will feature an extremely dynamic workload distribution where massive applications arranged as an unpredictable sequence enter and leave the system at run-time. Efficient mapping strategy is required to allocate system resources to the incoming application. Noncontiguous mapping improves system throughput by utilizing disjoint nodes, however, the increasing communication distance and external congestion lead to high power consumption and network delay. This paper thus presents an enhanced noncontiguous dynamic mapping algorithm, aiming at decreasing interprocessor communication overhead and improving both network and application performance. Communication volumes are utilized to arrange the mapping order of tasks belong to the same application. Moreover, expanding parameter of each task is developed which directs the optimized mapping decision comparing to the current neighborhood and occupancy information. Experimental results show that our modified mapping algorithm Weighted-based Neighborhood Allocation (WeNA) makes considerable improvements on Average Weighted Manhattan Distance (8.06%) and network latency (9.8%) in comparison with the state-of-the-art algorithm.
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| 5. |
- Pölzlbauer, Florian, et al.
(author)
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Optimised Frame Packing for Embedded Systems
- 2012
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In: Embedded Systems Letters. - 1943-0663. ; 4:3, s. 65-68
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Journal article (peer-reviewed)abstract
- During system synthesis (i.e., task allocation) the transmission of messages between tasks is usually addressed in a simplistic way. If a message is exchanged via an external bus, it is assumed each message is packed in an individual frame. This assumption leads to an overestimation of bus bandwidth demand and frameresponse time. For some systems (i.e., automotive), this pessimism is not acceptable and therefore frame packing is often performed where multiple messages are packed into a single frame. In this paper, an improved frame packing approach is provided.
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| 6. |
- Ren, Fengbo, et al.
(author)
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A Square-Root-Free Matrix Decomposition Method for Energy-Efficient Least Squares Computation on Embedded Systems
- 2014
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In: IEEE Embedded Systems Letters. - 1943-0663. ; 6:4, s. 73-76
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Journal article (peer-reviewed)abstract
- QR decomposition (QRD) is used to solve least squares (LS) problems for a wide range of applications. However, traditional QR decomposition methods, such as Gram-Schmidt (GS), require high computational complexity and non-linear operations to achieve high throughput, limiting their usage on resource-limited platforms. To enable efficient LS computation on embedded systems for real-time applications, this paper presents an alternative decomposition method, called QDRD, which relaxes system requirements while maintaining the same level of performance. Specifically, QDRD eliminates both the square-root operations in the normalization step and the divisions in the subsequent backward substitution. Simulation results show that the accuracy and reliability of factorization matrices can be significantly improved by QDRD, especially when executed on precision-limited platforms. Furthermore, benchmarking results on an embedded platform show that QDRD provides constantly better energy-efficiency and higher throughput than GS-QRD in solving LS problems. Up to 4 and 6.5 times improvement in energy-efficiency and throughput respectively can be achieved for small-size problems.
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