| 1. |
- Abedin, Ahmad, et al.
(author)
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Germanium on Insulator Fabrication for Monolithic 3-D Integration
- 2018
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In: IEEE Journal of the Electron Devices Society. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 2168-6734. ; 6:1, s. 588-593
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Journal article (peer-reviewed)abstract
- A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.
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| 2. |
- Asad, Muhammad, 1986, et al.
(author)
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The dependence of the high-frequency performance of graphene field-effect transistors on channel transport properties
- 2020
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In: IEEE Journal of the Electron Devices Society. - 2168-6734. ; 8, s. 457-464
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Journal article (peer-reviewed)abstract
- This paper addresses the high-frequency performance limitations of graphene field-effect transistors (GFETs) caused by material imperfections. To understand these limitations, we performed a comprehensive study of the relationship between the quality of graphene and surrounding materials and the high-frequency performance of GFETs fabricated on a silicon chip. We measured the transit frequency (fT) and the maximum frequency of oscillation (fmax) for a set of GFETs across the chip, and as a measure of the material quality, we chose low-field carrier mobility. The low-field mobility varied across the chip from 600 cm2/Vs to 2000 cm2/Vs, while the fT and fmax frequencies varied from 20 GHz to 37 GHz. The relationship between these frequencies and the low-field mobility was observed experimentally and explained using a methodology based on a small-signal equivalent circuit model with parameters extracted from the drain resistance model and the charge-carrier velocity saturation model. Sensitivity analysis clarified the effects of equivalent-circuit parameters on the fT and fmax frequencies. To improve the GFET high-frequency performance, the transconductance was the most critical parameter, which could be improved by increasing the charge-carrier saturation velocity by selecting adjacent dielectric materials with optical phonon energies higher than that of SiO2.
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| 3. |
- Chen, Xi, et al.
(author)
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Top-bottom gate coupling effect on low frequency noise in a Schottky junction gated silicon nanowire field-effect transistor
- 2019
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In: IEEE Journal of the Electron Devices Society. - 2168-6734. ; 7, s. 696-700
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Journal article (peer-reviewed)abstract
- In this letter, strong low frequency noise (LFN) reduction is observed when the buried oxide (BOX)/silicon interface of a Schottky junction gated silicon nanowire field-effect transistor (SJGFET) is depleted by a substrate bias. Such LFN reduction is mainly attributed to the dramatic reduction in Coulomb scattering when carriers are pushed away from the interface. The BOX/silicon interface depletion can also be achieved by sidewall Schottky junction gates in a narrow channel SJGFET, leading to an optimal LFN performance without the need of any substrate bias.
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| 4. |
- Dentoni Litta, Eugenio, et al.
(author)
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Enhanced channel mobility at sub-nm EOT by integration of a TmSiO interfacial layer in HfO2/TiN high-k/metal gate MOSFETs
- 2015
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In: IEEE Journal of the Electron Devices Society. - : IEEE conference proceedings. - 2168-6734. ; 3:5, s. 397-404
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Journal article (peer-reviewed)abstract
- Integration of a high-k interfacial layer (IL) is considered the leading technological solution to extend the scalability of Hf-based high-k/metal gate CMOS technology. We have previously shown that thulium silicate (TmSiO) IL can provide excellent electrical characteristics and enhanced channel mobility at sub-nm EOT. This paper presents a detailed analysis of channel mobility in TmSiO/HfO2/TiN MOSFETs, obtained through measurements at varying temperature and under constant voltage stress. We show experimentally for the first time that integration of a high-k IL can benefit mobility by attenuating remote phonon scattering. Specifically, integration of TmSiO results in attenuated remote phonon scattering compared to reference SiOx/HfO2 dielectric stacks having the same EOT, whereas it has no significant influence on remote Coulomb scattering.
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| 5. |
- Hou, Shuoben, et al.
(author)
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A Silicon Carbide 256 Pixel UV Image Sensor Array Operating at 400 degrees C
- 2020
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In: IEEE Journal of the Electron Devices Society. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 2168-6734. ; 8:1, s. 116-121
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Journal article (peer-reviewed)abstract
- An image sensor based on wide band gap silicon carbide (SiC) has the merits of high temperature operation and ultraviolet (UV) detection. To realize a SiC-based image sensor the challenge of opto-electronic on-chip integration of SiC photodetectors and digital electronic circuits must be addressed. Here, we demonstrate a novel SiC image sensor based on our in-house bipolar technology. The sensing part has 256 ( $16\times 16$ ) pixels. The digital circuit part for row and column selection contains two 4-to-16 decoders and one 8-bit counter. The digital circuits are designed in transistor-transistor logic (TTL). The entire circuit has 1959 transistors. It is the first demonstration of SiC opto-electronic on-chip integration. The function of the image sensor up to 400 degrees C has been verified by taking photos of the spatial patterns masked from UV light. The image sensor would play a significant role in UV photography, which has important applications in astronomy, clinics, combustion detection and art.
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| 6. |
- Hou, Shuoben, et al.
(author)
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Scaling and modeling of high temperature 4H-SiC p-i-n photodiodes
- 2018
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In: IEEE Journal of the Electron Devices Society. - : Institute of Electrical and Electronics Engineers Inc.. - 2168-6734. ; 6:1, s. 139-145
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Journal article (peer-reviewed)abstract
- 4H-SiC p-i-n photodiodes with various mesa areas (40,000μm2, 2500μm2, 1600μm2, and 400μm2) have been fabricated. Both C-V and I-V characteristics of the photodiodes have been measured at room temperature, 200 °C, 400 °C, and 500 °C. The capacitance and photo current (at 365 nm) of the photodiodes are directly proportional to the area. However, the dark current density increases as the device is scaled down due to the perimeter surface recombination effect. The photo to dark current ratio at the full depletion voltage of the intrinsic layer (-2.7 V) of the photodiode at 500 °C decreases 7 times as the size of the photodiode scales down 100 times. The static and dynamic behavior of the photodiodes are modeled with SPICE parameters at the four temperatures.
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| 7. |
- Hussain, Muhammad Waqar, 1985-, et al.
(author)
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A SiC BJT-Based Negative Resistance Oscillator for High-Temperature Applications
- 2019
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In: IEEE Journal of the Electron Devices Society. - : Institute of Electrical and Electronics Engineers (IEEE). - 2168-6734. ; 7:1, s. 191-195
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Journal article (peer-reviewed)abstract
- This brief presents a 59.5 MHz negative resistanceoscillator for high-temperature operation. The oscillator employs an in-house 4H-SiC BJT, integrated with the requiredcircuit passives on a low-temperature co-fired ceramic substrate. Measurements show that the oscillator operates from room-temperature up to 400 C. The oscillator delivers an output◦power of 11.2 dBm into a 50 Ω load at 25 C, which decreases to 8.4 dBm at 400 C. The oscillation frequency varies by 3.3% in the entire temperature range. The oscillator is biased witha collector current of 35 mA from a 12 V supply and has amaximum DC power consumption of 431 mW.
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| 8. |
- Kilpi, Olli Pekka, et al.
(author)
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Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs
- 2019
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In: IEEE Journal of the Electron Devices Society. - 2168-6734. ; 7, s. 70-75
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Journal article (peer-reviewed)abstract
- Vertical InAs/InGaAs nanowire MOSFETs are fabricated in a gate-last fabrication process, which allows gate-lengths down to 25 nm and accurate gate-alignment. These devices demonstrate high performance with transconductance of 2.4 mS/μm, high on-current, and off-current below 1 nA/μm. An in-depth analysis of the heterostructure MOSFETs are obtained by systematically varying the gate-length and gate location. Further analysis is done by using virtual source modeling. The injection velocities and transistor metrics are correlated with a quasi-ballistic 1-D MOSFET model. Based on our analysis, the observed performance improvements are related to the optimized gate-length, high injection velocity due to asymmetric scattering, and low access resistance.
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| 9. |
- Lee, Hsin Ying, et al.
(author)
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Fabrication and Characterization of GaN-Based Fin-Channel Array Metal-Oxide-Semiconductor High-Electron Mobility Transistors with Recessed-Gate and Ga2O3 Gate Insulator Layer
- 2021
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In: IEEE Journal of the Electron Devices Society. - 2168-6734. ; 9, s. 393-399
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Journal article (peer-reviewed)abstract
- In this work, the properties of gallium oxide (Ga2O3) and its excellent interface properties to GaN-based materials are explored as a gate insulator layer for GaN-based metal-oxide-semiconductor high-electron mobility transistors (MOSHEMTs). A novel vapor cooling condensation system was used to deposit the high quality Ga2O3 films with high insulation and low defect suitable for gate insulator layer. The characteristics of the Ga2O3 films were further explored by implementing GaN-based fin-channel array MOSHEMTs with recessed-gates and different channel widths. Compared to planar channel structure, the direct current, high frequency, and flicker noise performances were enhanced in the fin-channel MOSHEMTs with Ga2O3 gate insulator layer. For the GaN-based fin-channel array MOSHEMTs with 300-nm-wide channel, the devices exhibited superior performances of maximum extrinsic transconductance of 194.2 mS/mm, threshold voltage of.1.4 V, extrinsic unit gain cutoff frequency of 6.4 GHz, maximum oscillation frequency of 14.8 GHz, and normalized noise power of 8.45 × 10.15 Hz.1. It was also demonstrated that the associated performances were improved by reducing the width of fin-channel array.
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| 10. |
- Li, Junjie, 1995, et al.
(author)
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Investigation of Noise Properties in the InP HEMT for LNAs in Qubit Amplification: Effects From Channel Indium Content
- 2024
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In: IEEE Journal of the Electron Devices Society. - 2168-6734. ; 12, s. 243-248
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Journal article (peer-reviewed)abstract
- The InP high-electron-mobility transistor (HEMT) is employed in cryogenic low-noise amplifiers (LNAs) for the readout of faint microwave signals in quantum computing. The performance of such LNAs is ultimately limited by the properties of the active InxGa1-xAs channel in the InP HEMT. In this study, we have investigated the noise performance of 100-nm gate-length InP HEMTs used in cryogenic LNAs for amplification of qubits. The channel indium content in the InP HEMTs was 53, 60 and 70%. Hall measurements of the epitaxial materials and dc characterization of the InP HEMTs confirmed the superior transport properties of the channel structures. An indirect method involving an LNA and small-signal noise modeling was used for extracting the channel noise with high accuracy. Under noise-optimized bias, we observed that the 60% indium channel InP HEMT exhibited the lowest drain noise temperature. The difference in LNA noise temperature among InP HEMTs became more pronounced with decreasing drain voltage and current. An average noise temperature and average gain of 3.3 K and 21 dB, respectively, for a 4-8 GHz three-stage hybrid cryogenic LNA using 60% indium channel InP HEMTs was measured at a dc power consumption of 108 μW. To the best of the authors’ knowledge, this is a new state-of-the-art for a C-band LNA operating below 1 mW. The higher drain noise temperature observed for 53 and 70% indium channels InP HEMTs can be attributed to a combination of thermal noise in the channel and real-space transfer of electrons from the channel to the barrier. This report gives experimental evidence of an optimum channel indium content in the InP HEMT used in LNAs for qubit amplification.
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