| 1. |
- Svensson, Christer, et al.
(author)
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Resource efficient implementation of a 10Gb/s radio receiver baseband in FPGA
- 2013
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In: 10th FPGAworld Conference - Academic Proceedings 2013, FPGAworld 2013. Stockholm, Sweden; 10-12 September 2013.. - New York, NY, USA : ACM. - 9781450324960
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Conference paper (peer-reviewed)abstract
- Data-rate of wireless links are increasing fast, particularly when new carrier bands with very high bandwidth becomes available. Utilizing the full bandwidth for a single carrier facilitates very large baud-rates. When the baud-rates approaches or exceeds Gbaud, the implementation of the digital baseband is no longer a simple extension of existing methods. In the present paper we propose a resource efficient implementation of digital baseband for multi-Gbaud rates in a standard FPGA utilizing Xilinx Simulink-based System generator design and verification tool. Copyright 2010 ACM.
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| 2. |
- Uddin, Saif, et al.
(author)
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An improved transmission scheme for error-prone inter-chip Network-on-Chip communication links implemented on FPGAs
- 2013
-
In: 10th FPGAworld Conference - Academic Proceedings 2013, FPGAworld 2013. - New York, NY, USA : ACM. - 9781450324960
-
Conference paper (peer-reviewed)abstract
- Network-on-Chip (NoC) is an alternative to traditional busses for faster interconnect mechanism. The aim is to have infinite scalability, and this implies the possibility to extend the on-chip NoC communication protocol off-chip. To gain wholesome advantage of Network-on-Chip (NoC), off-chip extensions should also have similar communication throughput compared to the on-chip network. Faster data-rate is the single most demanded requirement of modern applications. There is a continuous drive to fulfill this escalating demand as much as possible. Two of the most prominent limiting factors in achieving this purpose are 'reduced accuracy' and 'protocol handling', especially in case of systems which do not have synchronous communication. Efficient optimizations are needed in multiple areas to upgrade the speed of data transfer. This paper presents an improved off-chip network solution to a slower and error-prone board-bridge part of a Network-on-Chip (NoC). The new solution increases the accuracy and speed of the plesiochronous off-chip extension to the NoC. The Network-on-Chip has 16 processor-nodes implemented on four interconnected plesiochronous Altera Stratix-II FPGA boards in 4x4 configuration in such a way that each board hosts a Quad-core NoC.
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