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Search: L773:9781467315869

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  • Mohammadi, Babak, et al. (author)
  • Sizing of Dual-V-T Gates for Sub-V-T Circuits
  • 2012
  • In: 2012 IEEE Subthreshold Microelectronics Conference (SubVT). - 9781467315869
  • Conference paper (peer-reviewed)abstract
    • This paper presents a novel method to improve the performance of sub-threshold (sub-V-T) gates in 65-nm CMOS technology. Faster transistors with a lower threshold voltage are introduced in the weaker network of a gate. It is shown that the employed method significantly enhances the reliability and performance of the gate, with an additive advantage of a lower area cost compared to traditional transistor sizing. Extensive Monte-Carlo simulations are carried out to verify the proposed optimization technique. The simulation results predict that the NAND3 and NOR3 testbench shows a 98% higher noise margin. Furthermore, the inverter and NAND3 gates show an speed improvement of 48% and 97%, respectively.
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  • Result 1-3 of 3
Type of publication
conference paper (3)
Type of content
peer-reviewed (3)
Author/Editor
Rodrigues, Joachim (3)
Mohammadi, Babak (1)
Sparsø, Jens (1)
Edfors, Ove (1)
Andersson, Oskar (1)
Sherazi, Syed Muhamm ... (1)
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Karlsson, Andreas (1)
Seyed Mazloum, Nafis ... (1)
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University
Lund University (3)
Language
English (3)
Research subject (UKÄ/SCB)
Engineering and Technology (3)
Year
2012 (3)

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