| 1. |
- Majd, Amin, et al.
(author)
-
PICA : Multi-Population Implementation of Parallel Imperialist Competitive Algorithms
- 2016
-
In: 2016 24TH EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, AND NETWORK-BASED PROCESSING (PDP). - : Institute of Electrical and Electronics Engineers (IEEE). - 9781467387767 ; , s. 248-255
-
Conference paper (peer-reviewed)abstract
- The importance of optimization and NP problems solving cannot be over emphasized. The usefulness and popularity of evolutionary computing methods are also well established. There are various types of evolutionary methods that arc mostly sequential, and some others have parallel implementation. We propose a method to parallelize Imperialist Competitive Algorithm (Multi-Population). The algorithm has been implemented with MPI on two platforms and have tested our algorithms on a shared- memory and message passing architecture. An outstanding performance is obtained, which indicates that the method is efficient concern to speed and accuracy. In the second step, the proposed algorithm is compared with a set of existing well known parallel algorithms and is indicated that it obtains more accurate solutions in a lower time.
|
|
| 2. |
- Rezaei, Amin, et al.
(author)
-
Efficient Congestion-Aware Scheme for Wireless On-Chip Networks
- 2016
-
In: 2016 24TH EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, AND NETWORK-BASED PROCESSING (PDP). - : Institute of Electrical and Electronics Engineers (IEEE). - 9781467387767 ; , s. 742-749
-
Conference paper (peer-reviewed)abstract
- Wireless NoC is becoming popular to be a promising future on-chip interconnection network as a result of high bandwidth, low latency and flexible topology configurations provided by this emerging technology. Nonetheless, congestion occurrence in wireless routers negatively affects the usability of high speed wireless links and considerably increases the network latency; therefore, in this paper, a congestion-aware platform (CAP-W) is introduced for wireless NoCs in order to reduce both internal and external congestions. The whole platform of CAP-W consists of an adaptive routing algorithm that balances utilization of wired and wireless networks, a dynamic task mapping approach that tries to minimize congestion probability, and a task migration strategy that considers dynamic variation of application behaviors. Simulation results show significant gain in congestion control over PEs of wireless NoC, compared to state-of-the-art works.
|
|
| 3. |
- Rezaei, Seyyed Hossein Seyyedaghaei, et al.
(author)
-
A Three-Dimensional Networks-on-Chip Architecture with Dynamic Buffer Sharing
- 2016
-
In: 2016 24TH EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, AND NETWORK-BASED PROCESSING (PDP). - 9781467387767 ; , s. 771-776
-
Conference paper (peer-reviewed)abstract
- 3D integration is a practical solution for overcoming the failure of Dennard scaling in future technology generations. This emerging technology stacks several die slices on top of each other on a single chip in order to provide higher-bandwidth and lower-latency than a 2D design due to extremely shorter inter-layer distances in the third dimension and. In this paper, we leverage the low latency vertical links to address buffer management, one of the most important design and management issues in Network-on-Chip(NoC). To this end, we present VerBuS, an architecture for 3D routers with Vertical BUffer Sharing capability enabled by ultra-low latency vertical links of a 3D chip. VerBuS can share virtual channels (VC) between vertically stacked routers. This way, the buffering capacity of a highly loaded router is increased by using idle VCs of vertically adjacent routers. Experimental results show up to 20% improvement in NoC performance metrics over state-of-the-art 3D router designs.
|
|
| 4. |
- Thorarensen, Sebastian, et al.
(author)
-
Efficient Execution of SkePU Skeleton Programs on the Low-power Multicore Processor Myriad2
- 2016
-
In: 2016 24TH EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, AND NETWORK-BASED PROCESSING (PDP). - : IEEE. - 9781467387767 ; , s. 398-402
-
Conference paper (peer-reviewed)abstract
- SkePU is a state-of-the-art skeleton programming library for high-level portable programming and efficient execution on heterogeneous parallel computer systems, with a publically available implementation for general-purpose multicore CPU and multi-GPU systems. This paper presents the design, implementation and evaluation of a new back-end of the SkePU skeleton programming library for the new low-power multicore processor Myriad2 by Movidius Ltd. This enables seamless code portability of SkePU applications across both HPC and embedded (Myriad2) parallel computing systems, with decent performance, on these architecturally very diverse types of execution platforms.
|
|
