| 1. |
- Cantoro, R., et al.
(författare)
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On the diagnostic analysis of IEEE 1687 networks
- 2016
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Ingår i: Proceedings - 2016 21st IEEE European Test Symposium, ETS 2016. - 9781467396592
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Konferensbidrag (refereegranskat)abstract
- The IEEE 1687 standard describes reconfigurable structures allowing to flexibly access the instruments existing within devices (e.g., to support test, diagnosis, calibration, etc.), by using configuration modules which act as controllable switches. The increasing adoption of this standard requires the availability of algorithms and tools to automate its usage. The resulting networks might be affected by defects preventing their correct operation. This necessitates the availability of solutions which allow not only to test against defects, but also to identify the location of possible faults via diagnosis. This paper for the first time addresses the problem of the diagnosis of IEEE 1687 networks. Experimental results gathered on a set of benchmark networks show the feasibility of the solution and provide a first idea about the length of the required input stimuli.
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| 2. |
- Ghani Zadegan, Farrokh, et al.
(författare)
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A Self-Reconfiguring IEEE 1687 Network for Fault Monitoring
- 2016
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Ingår i: 21th IEEE European Test Symposium (ETS), 2016. - 9781467396592
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Konferensbidrag (refereegranskat)abstract
- Efficient handling of faults during operation is highly dependent on the interval (latency) from the time embedded instruments detect errors to the time when the fault manager localizes the errors. In this paper, we propose a self-reconfiguring IEEE 1687 network in which all instruments that have detected errors are automatically included in the scan path. To enable self-reconfiguration, we propose a modified segment insertion bit (SIB) compliant to IEEE 1687. We provide time analyses on error detection and fault localization for single and multiple faults, and we suggest how the self-reconfiguring IEEE 1687 network should be designed such that time for error detection and fault localization is kept low and deterministic. For validation, we implemented and performed post-layout simulations for one self-reconfiguring network. We show that compared to previous schemes, our proposed network significantly reduces the fault localization time.
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| 3. |
- Zhang, Jing, et al.
(författare)
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Compressor design for silicon debug
- 2016
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Ingår i: Proceedings - 2016 21st IEEE European Test Symposium, ETS 2016. - 9781467396592
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Konferensbidrag (refereegranskat)abstract
- The objective of this paper is to design a compressor for silicon debug that is suitable in an industrial Nexus environment. The compressor must operate in real-time and must be lossless. Important for the compressor is high compression ratio, low hardware cost and high throughput. We implemented the compression on an FPGA and we compared our implementation in terms of throughput and hardware cost against other approaches.
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