| 1. |
- Abdullah, Jakaria, et al.
(author)
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Worst-Case Cause-Effect Reaction Latency in Systems with Non-Blocking Communication
- 2019
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In: Design, Automation & Test in Europe Conference & Exhibition. - : IEEE. - 9783981926323 ; , s. 1625-1630
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Conference paper (peer-reviewed)abstract
- In real-time embedded systems, a system functionality is often implemented using a data-flow chain over a set of communicating tasks. A critical non-functional requirement in such systems is to restrict the amount of time, i.e. cause-effect latency, for an input to impact its corresponding output. The problem of estimating the worst-case cause-effect latency is well-studied in the context of blocking inter-task communication. Recent research results show that non-blocking communication preserving functional semantics is critical for the model-based design of dynamically updatable systems. In this paper, we study the worst-case cause-effect reaction latency estimation problem in the context of non-blocking inter-task communication. We present a computationally efficient algorithm that tightly over-approximates the exact worst-case reaction latency in cause-effect data-flow chains.
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| 2. |
- Alipour, Mehdi, et al.
(author)
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FIFOrder MicroArchitecture : Ready-Aware Instruction Scheduling for OoO Processors
- 2019
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In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). - : IEEE. - 9783981926323 ; , s. 716-721
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Conference paper (peer-reviewed)abstract
- The number of instructions a processor's instruction queue can examine (depth) and the number it can issue together (width) determine its ability to take advantage of the ILP in an application. Unfortunately, increasing either the width or depth of the instruction queue is very costly due to the content-addressable logic needed to wakeup and select instructions out-of-order. This work makes the observation that a large number of instructions have both operands ready at dispatch, and therefore do not benefit from out-of-order scheduling. We leverage this to place such ready-at-dispatch instructions in separate, simpler, in-order FIFO queues for scheduling. With such additional queues, we can reduce the size and width of the expensive out-of-order instruction queue, without reducing the processor's overall issue width and depth. Our design, FIFOrder, is able to steer more than 60% of instructions to the cheaper FIFO queues, providing a 50% energy savings over a traditional out-of-order instruction queue design, while delivering 8% higher performance.
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| 3. |
- Chen, Zhongsheng, et al.
(author)
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A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Wafer-Level NoC
- 2019
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In: 2019 DESIGN, AUTOMATION and TEST IN EUROPE CONFERENCE and EXHIBITION (DATE). - : IEEE. - 9783981926323 - 9781728103310 ; , s. 1337-1342
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Conference paper (peer-reviewed)abstract
- Wafer-level NoC has emerged as a promising fabric to further improve supercomputer performance, but this new fabric may suffer from the many-fault problem. This paper presents a deterministic-path routing algorithm for tolerating many faults on wafer-level NoCs. The proposed algorithm generates routing tables using a breadth-first traversal strategy, and stores one routing table in each NoC switch. The switch will then transmit packages according to its routing table online. We use the Tarjan algorithm to dynamically reconfigure the routes to avoid the faulty nodes and develop the deprecated link/node rules to ensure deadlock-free communication of the NoCs. Experimental results demonstrate that the proposed algorithm does not only tolerate the effects of many faults, but also maximizes the available nodes in the reconfigured NoC. The performance of the proposed algorithm in terms of average latency, throughput, and energy consumption is also better than those of the existing solutions.
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| 4. |
- Liu, Weihua, et al.
(author)
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Characterizing the Reliability and Threshold Voltage Shifting of 3D Charge Trap NAND Flash
- 2019
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In: 2019 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE). - : IEEE. - 9783981926323 ; , s. 312-315
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Conference paper (peer-reviewed)abstract
- 3D charge trap (CT) triple-level cell (TLC) NAND flash gradually becomes a mainstream storage component due to high storage capacity and performance, but introducing a concern about reliability. Fault tolerance and data management schemes are capable of improving reliability. Designing a more efficient solution, however, needs to understand the reliability characteristics of 3D CT TLC NAND flash. To facilitate such understanding, by exploiting a real-world testing platform, we investigate the reliability characteristics including the raw bit error rate (RBER) and the threshold voltage (Vth) shifting features after suffering from variable disturbances. We give analyses of why these characteristics exist in 3D CT TLC NAND flash. We hope these observations can guide the designers to propose high efficient solutions to the reliability problem.
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| 5. |
- Maghazeh, Arian, et al.
(author)
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Cache-Aware Kernel Tiling: An Approach for System-Level Performance Optimization of GPU-Based Applications
- 2019
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In: 2019 DESIGN, AUTOMATION and TEST IN EUROPE CONFERENCE and EXHIBITION (DATE). - : IEEE. - 9783981926323 ; , s. 570-575
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Conference paper (peer-reviewed)abstract
- We present a software approach to address the data latency issue for certain GPU applications. Each application is modeled as a kernel graph, where the nodes represent individual GPU kernels and the edges capture data dependencies. Our technique exploits the GPU L2 cache to accelerate parameter passing between the kernels. The key idea is that, instead of having each kernel process the entire input in one invocation, we subdivide the input into fragments (which fit in the cache) and, ideally, process each fragment in one continuous sequence of kernel invocations. Our proposed technique is oblivious to kernel functionalities and requires minimal source code modification. We demonstrate our technique on a full-fledged image processing application and improve the performance on average by 30% over various settings.
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| 6. |
- Park, Taeju, et al.
(author)
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Design Optimization of Frame Preemption in Real-Time Switched Ethernet
- 2019
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In: 2019 DESIGN, AUTOMATION and TEST IN EUROPE CONFERENCE and EXHIBITION (DATE). - : IEEE. - 9783981926323 ; , s. 420-425
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Conference paper (peer-reviewed)abstract
- Switched Ethernet has been, and will also be increasingly common in current and future real-time and embedded systems. The IEEE 802.1 working group has recently developed standards and technologies, commonly referred to as Time-Sensitive Networking (TSN), to enhance switched Ethernet with timeliness and dependability. We address, for the first time, the synthesis problem for the TSN frame preemption standards IEEE 802.3br-2016 and 802.1Qbu-2016 by introducing two new configuration parameters: flow to queue and queue to Express/Preemptable MAC interface assignments. We present an optimization framework to determine these configuration parameters with reliability as the optimization goal. Our proposed framework is shown to outperform commonly used priority-assignment as well as intuitive approaches.
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| 7. |
- Sadovykh, A., et al.
(author)
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On the Use of Hackathons to Enhance Collaboration in Large Collaborative Projects : - A Preliminary Case Study of the MegaM@Rt2 EU Project - A P
- 2019
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In: Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019. - : Institute of Electrical and Electronics Engineers Inc.. - 9783981926323 ; , s. 498-503
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Conference paper (peer-reviewed)abstract
- In this paper, we present the MegaM@Rt2 ECSEL project and discuss in details our approach for fostering collaboration in this project. We choose to use an internal hackathon approach that focuses on technical collaboration between case study owners and tool/method providers. The novelty of the approach is that we organize the technical workshop at our regular project progress meetings as a challenge-based contest involving all partners in the project. Case study partners submit their challenges related to the project goals and their use cases in advance. These challenges are concise enough to be experimented within approximately 4 hours. Teams are then formed to address those challenges. The teams include tool/method providers, case study owners and researchers/developers from other consortium members. On the hackathon day, partners work together to come with results addressing the challenges that are both interesting to encourage collaboration and convincing to continue further deeper investigations. Obtained results demonstrate that the hackathon approach stimulated knowledge exchanges among project partners and triggered new collaborations, notably between tool providers and use case owners.
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| 8. |
- Wang, Boqian, et al.
(author)
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Advance Virtual Channel Reservation
- 2019
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In: 2019 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE). - : IEEE. - 9783981926323 ; , s. 1178-1183
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Conference paper (peer-reviewed)abstract
- We present a smart communication service called Advance Virtual Channel Reservation (AVCR) to provide a highway to packets, which can greatly reduce their contention delay in NoC. AVCR takes advantage of the fact that we can know or predict the destination of some packets ahead at the network interface (NI). Exploiting the time slack before a packet is ready, AVCR establishes an end-to-end highway from the source NI to the destination NI. This highway is built up by reserving virtual channel (VC) resources ahead and at the same time, offering priority service to those VCs in the router, which can therefore avoid highway packets' VC allocation and switch arbitration delay in NoC. Additionally, optimization schemes are developed to reduce VC overhead and increase highway utilization. We evaluate AVCR with cycle-accurate full-system simulations in GEM5 by using all benchmarks in PARSEC. Compared to the state-of-art mechanisms and the priority based mechanism, experimental results show that our mechanism can significantly reduce the target packets' transfer latency and effectively decrease the average region-of-interest (ROI) time by 22.4% (maximally by 29.4%) across PARSEC benchmarks.
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