| 1. |
- Bayona, Jhon F., et al.
(author)
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Linear Control of a Power Factor Correction Rectifier in Half-bridge Configuration
- 2016
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In: IEEE CACIDI 2016 - IEEE CONFERENCE ON COMPUTER SCIENCES. - : IEEE. - 9781509029389
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Conference paper (peer-reviewed)abstract
- This paper presents a detailed analysis of a single phase high power factor boost half-bridge rectifier (RPFU-HBB). The purpose of this work is to achieve a unity power factor with tight-regulated output voltage. Using the experimental prototype for 120 Vrms input voltage, output power 80W and output voltage of 450V; a power factor of 0.99 and total harmonic distortion of 2.5% was obtained. In order to eliminate the unbalance voltage of the two output capacitors a special control scheme was developed. Modeling, theoretical linearization around the operating point of the RPFU-HBB, design considerations of the current controller output voltage by means of average current method and experimental work tested through simulation model RPFU-HBB are presented.
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| 2. |
- Chamorro, H. R., et al.
(author)
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Data-driven trajectory prediction of grid power frequency based on neural models
- 2021
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In: Electronics. - : MDPI AG. - 2079-9292. ; 10:2
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Journal article (peer-reviewed)abstract
- Frequency in power systems is a real-time information that shows the balance between generation and demand. Good system frequency observation is vital for system security and pro-tection. This paper analyses the system frequency response following disturbances and proposes a data-driven approach for predicting it by using machine learning techniques like Nonlinear Autoregressive (NAR) Neural Networks (NN) and Long Short Term Memory (LSTM) networks from simulated and measured Phasor Measurement Unit (PMU) data. The proposed method uses a horizon-window that reconstructs the frequency input time-series data in order to predict the frequency features such as Nadir. Simulated scenarios are based on the gradual inertia reduction by including non-synchronous generation into the Nordic 32 test system, whereas the PMU collected data is taken from different locations in the Nordic Power System (NPS). Several horizon-windows are experimented in order to observe an adequate margin of prediction. Scenarios considering noisy signals are also evaluated in order to provide a robustness index of predictability. Results show the proper performance of the method and the adequate level of prediction based on the Root Mean Squared Error (RMSE) index. © 2021 by the authors.
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| 3. |
- Dominguez-Bonilla, Camilo, et al.
(författare)
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SysML Methodology for FPGA-based Controller Design for Quadcopters
- 2016
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Ingår i: 7TH IEEE ANNUAL INFORMATION TECHNOLOGY, ELECTRONICS & MOBILE COMMUNICATION CONFERENCE IEEE IEMCON-2016. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781509009961
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Konferensbidrag (refereegranskat)abstract
- In this paper an Integrated Development Environment (IDE) is proposed for the FPGA Controller design for quadcopters (including specifications, design and implementa-tion). This IDE was developed using the High Level Specification of Embedded Systems Rich Client Platform (HiLeS-RCP). The HiLeS-RCP is a framework for specialized "per product line" IDE construction, which links requirements formalization step that represents the structural modelling using SysML, and the virtual prototyping. In this work the product line corresponds to flight controllers for quadcopters. This specialized IDE allows to manage the complexity of designs and to reduce development time for a modular implementation in Hardware Description Language (HDL).
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| 4. |
- Gutierrez, A., et al.
(författare)
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Hardware-in-the-loop simulation of PV systems in micro-grids using SysML models
- 2015
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Ingår i: 2015 IEEE 16th Workshop on Control and Modeling for Power Electronics. - : IEEE. - 9781467368476
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Konferensbidrag (refereegranskat)abstract
- This paper outlines a methodology for modeling photovoltaic systems in embedded hardware. This methodology uses the HiLeS platform to transform SysML models in Petri nets and generate VHDL code. The proposed methodology is intended for Hardware-in-the-Loop simulations of power converters and PV panels in microgrids. In addition, this methodology allows the design of MPPT controllers for their direct implementation in FPGA.
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| 5. |
- Gutierrez, A., et al.
(författare)
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Supervisory Control for Interleaved Boost Converters using HiLeS-Designer
- 2014
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Ingår i: 2014 16TH EUROPEAN CONFERENCE ON POWER ELECTRONICS AND APPLICATIONS (EPE'14-ECCE EUROPE). - : IEEE Press.
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Konferensbidrag (refereegranskat)abstract
- This paper presents the application of HiLeS (High Level Specification of Embedded Systems) formalism to design a supervisory controller based on FPGA for interleaved boost converters. This controller is intended to increase the versatility and efficiency of interleaved boost converters. Furthermore, the proposed supervisory controller uses Petri nets for structural analysis and stability. HiLeS-Designer tool, which is a platform based on HiLeS formalism, is used to design and implement the supervisory controller in embedded hardware. This approach uses the digital component of VHDL-AMS code generated by the HiLeS-Designer tool to implement the supervisory controller in FPGA. Simulations and experimental results show that the proposed control strategy increases the operating range and efficiency of interleaved boost converters.
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| 6. |
- Gutierrez, A., et al.
(författare)
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SysML Methodology for HIL Implementation of PV Models
- 2015
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Ingår i: 2015 17TH EUROPEAN CONFERENCE ON POWER ELECTRONICS AND APPLICATIONS (EPE'15 ECCE-EUROPE). - : IEEE. - 9789075815238
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Konferensbidrag (refereegranskat)abstract
- This paper describes a methodology for implementing in FPGA models of photovoltaic panels for Hardware-in-the-Loop (HIL) and real-time simulations. The proposed methodology integrates numerical solutions, SysML diagrams and Petri nets for structural design and formal validation. In this study, photovoltaic cells have been modeled using the single diode circuit. The photovoltaic panel model is solved by the Newton-Raphson method, and the Lagrange remainder is employed to limit the iteration number. Results show suitable accuracy and performance of the proposed methodology.
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