1. |
- Bassoo, Vandana, et al.
(author)
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A potential transmitter architecture for future generation green wireless base station
- 2009
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In: Eurasip Journal on Wireless Communications and Networking. - : Springer Science and Business Media LLC. - 1687-1472 .- 1687-1499. ; :doi:10.1155/2009/821846
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Journal article (peer-reviewed)abstract
- Current radio frequency power amplifiers in 3G base stations have very high power consumption leading to a hefty cost and negative environmental impact. In this paper, we propose a potential architecture design for future wireless base station. Issues associated with components of the architecture are investigated. The all-digital transmitter architecture uses a combination of envelope elimination and restoration (EER) and pulse width modulation(PWM)/ pulse position modulation (PPM). The performance of this architecture is predicted from the measured output power and efficiency curves of a GaN amplifier. 57% efficiency is obtained for an OFDM signal limited to 8dB peak to average power ratio. The PWM/PPM drive signal is generated using the improved Cartesian sigma delta techniques. It is shown that an RF oversampling by a factor of four meets the WLAN spectral mask and WCDMA specification is met by an RF oversampling of sixteen.
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2. |
- Bassoo, Vandana, et al.
(author)
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Potential Architecture for Future Generation "Green" Wireless Base Station
- 2009
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In: 4th International Symposium on Wireless and Pervasive Computing (ISWPC) 2009. - : IEEE. - 9781424429653 - 9781424429660
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Conference paper (peer-reviewed)abstract
- Current radio frequency power amplifiers (PAs) in 3G base stations have very high power consumption leading to a hefty cost and negative environmental impact. In this paper, we propose a potential architecture design for future wireless base station. Issues associated with components of the architecture are investigated. A comparison of PA with pulse width modulation drive and PA with envelope elimination and restoration (EER) drive is offered. EER-driven PA promises high efficiency over a wide dynamic range but has bandwidth expansion problems. A novel approach which reduces bandwidth expansion on the envelope by 54% is proposed. A modulator is used to convert amplitude and phase information into the edges of a pulse train. The modulator also eradicates some analog components present in traditional base station design.
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3. |
- Cijvat, Ellie, et al.
(author)
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CMOS Transceiver Front-Ends in Mobile Communication Handsets : Architectures and Building Blocks
- 2004
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Doctoral thesis (other academic/artistic)abstract
- For mobile communication systems in the low-GHz range, CMOS has increasingly become the technology of choice, and the level of integration in mobile handsets has risen. The use of off-chip components, which increases the handset assembly time and costs, is preferably avoided. However, integrating a complete transceiver on a single chip leads to disturbances between building blocks. This imposes new and more stringent requirements on building block and transceiver performance, as well as impacts the choice of transceiver architecture.In the general introduction, an overview is given of front-end receiver and transmitter aspects as well as RF CMOS technology. This includes the impact of mobile communication system specifications on architectures and building blocks, transistor and monolithic inductor modeling, and disturbance issues. Special attention is given to power amplifiers, the most challenging building blocks in CMOS transceivers. Papers I, II and III address CMOS receiver front-end aspects and implementations, while in papers IV and V design and challenges of CMOS power amplifiers are described.
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4. |
- Cijvat, Pieternella, et al.
(author)
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A 2.4 GHz CMOS power amplifier using internal frequency doubling
- 2005
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In: 2005 IEEE International Symposium On Circuits And Systems (Iscas), Vols 1-6, Conference Proceedings. - Kobe, Japan : IEEE Press. - 0780388348 ; , s. 2683-2686
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Conference paper (peer-reviewed)abstract
- A fully integrated 0.18 μm 1P6M CMOS power amplifier using internal frequency doubling is presented. Two chips were measured, one stand-alone PA and one PA with a VCO on the same chip. Since the PA and VCO operate at different frequencies, this configuration is suitable for direct-upconversion or low-IF upconversion since oscillator pulling is reduced. The maximum output power is 15 dBm, and the maximum drain efficiency is 10.7% at an output operating frequency of 2.4 GHz
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5. |
- Cijvat, Pieternella, et al.
(author)
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A comparison of polar transmitter architectures using a GaN HEMT power amplifier
- 2008
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Conference paper (peer-reviewed)abstract
- In this paper three transmitter architectures are compared, that each use the low-frequency envelope and high-frequency phase component of an RF signal. A power amplifier (PA) with Pulse Width Modulation by Variable Gate Bias (PWMVGB) is compared to an Envelope Elimination and Restoration (EER) and Envelope Tracking (ET) configuration. The test circuit is implemented using a discrete GaN HEMT power amplifier and discrete surface-mount passive components assembled on a PCB. Measurements show that the EER architecture maintains a drain efficiency of 56 to 69% for a wide output power range, while the PA with variable gate bias shows a significant drop in efficiency for lower output powers (from 59 to 6%). Other comparison issues are modulation of the supply voltage and transmitter complexity.
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6. |
- Cijvat, Pieternella, et al.
(author)
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A fully integrated 2.45 GHz 0.25 mu m CMOS power amplifier
- 2003
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In: Proceedings of the 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2003.. - : IEEE Press. - 0780381637 ; , s. 1094-1097
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Conference paper (peer-reviewed)abstract
- A fully integrated differential class-AB power amplifier has been designed in a 0.25 um CMOS technology. It is intended for medium output power ranges such as Bluetooth class 1, and has an operating frequency of 2.45 GHz. By using two parallel output stages that can be switched on or off, a high efficiency can be achieved for both high and low output power levels. The simulated maximum output power is 22.7 dBm, while the maximum power-added efficiency is 22%.
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7. |
- Cijvat, Pieternella, et al.
(author)
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A GaN HEMT power amplifier with variable gate bias for envelope and phase signals
- 2007
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In: [Host publication title missing]. - Aalborg, Denmark : Institute of Electrical and Electronics Engineers (IEEE). - 9781424415168 ; , s. 108-111
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Conference paper (peer-reviewed)abstract
- This paper describes the design, simulation and measurement of a GaN power amplifier suitable for envelope and phase signal combination. The low-frequency envelope signal is used to vary the gate (bias) voltage of the device, resulting in a pulse width modulated drain voltage, while modulation of supply voltage or current is avoided. The test circuit is implemented using a discrete GaN HEMT power amplifier and discrete surface-mount passive components assembled on a PCB. Measurements showed a maximum drain efficiency of 59% at 360 MHz, at an output power of 29 dBm. The output power as a function of the gate bias voltage varied between 3 and 29 dBm, with the drain efficiency varying between 6 and 59%.
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8. |
- Cijvat, Pieternella, et al.
(author)
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Two 130nm CMOS class-D RF power amplifiers suitable for polar transmitter architectures
- 2008
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In: - : IEEE Press. ; , s. 1372-1375
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Conference paper (peer-reviewed)abstract
- Two class-D RF power amplifiers consisting of CMOS inverter chains have been designed and measured. The first amplifier operates at 1GHz and has a maximum output power of 12dBm, whereas the second operates at 1.5GHz and outputs a maximum of 6dBm. The amplifiers have been characterized for use in two different polar transmitter architectures, Pulse Width Modulation by Variable Gate Bias (PWMVGB) and Envelope Elimination and Restoration (EER). Using a standard 130nm digital CMOS process and off-chip passive components, maximum drain efficiencies of 32% and 39%, respectively, are achieved. The two amplifiers are compared with respect to output power and drain efficiency, including a qualitative analysis of losses. Moreover, their use in the two polar transmitter architectures is discussed.
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9. |
- Liakos, Evangelos, et al.
(author)
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Benefits of implementing a duty-ratio controlled parallel-resonant converter with SiC MOSFETs instead of Si IGBTs
- 2021
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In: 2021 23rd European Conference on Power Electronics and Applications, EPE 2021 ECCE Europe. - : IEEE. - 9789075815375
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Conference paper (peer-reviewed)abstract
- In this paper, the operation of a parallel resonant converter with a capacitive output filter that exploits the parasitic components of its transformer is described briefly. Measurements from a high power DC pulsed generator with Si IGBTs are obtained. Finally, the experimentally calculated losses of the Si IGBTs are compared with SiC MOSFETs' losses using simulations of the system. © 2021 EPE Association.
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