| 1. |
- Ingelsson, Urban, et al.
(author)
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Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption
- 2015
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In: IEEE Transactions on Computers. - 0018-9340. ; 64:12, s. 3335-3347
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Journal article (peer-reviewed)abstract
- System-on-chips (SOCs) and 3D stacked ICs are often tested for manufacturing defects in a modular fashion, enabling us to record the module test pass probability. We use this pass probability to exploit the abort-on-fail feature of automatic test equipment (ATE) and hence reduce the expected test time in the context of single-site testing. We present a model for calculation of expected test time, for which the abortable test unit can be a module test, a test pattern or a clock cycle. Given an SOC, with test architecture consisting of module test wrappers and test access mechanisms (TAMs), and given module test pass probabilities, we schedule the tests on each TAM to minimize the expected test time. We describe four scheduling heuristics, one without and three with preemption. Experimental results for the ITC’02 SOC Test Benchmarks show 3.5% and 20% reduction of expected test time in SOCs with 0.89 and 0.71 SOC test pass probability respectively, without modification of SOC or ATE. Further experiments show how accurate estimates for the module test pass probability or the distribution of pass probability over test patterns need to be to lead to effective test schedulng.
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| 2. |
- Ingelsson, Urban, et al.
(author)
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Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
- 2005
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In: IEEE European Test Symposium ETS 05,2005. - Tallinn, Estonia : IEEE Computer Society Press.
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Conference paper (peer-reviewed)abstract
- Complex SOCs are increasingly tested in a modular fashion, which enables us to record the yield-per-module. In this paper, we consider the yield-per-module as the pass probability of the module s manufacturing test. We use it to exploit the abort-on-fail feature of ATEs, in order to reduce the expected test application time. We present a model for expected test application time, which obtains increasing accuracy due to decreasing granularity of the abortable test unit. For a given SOC, with a modular test architecture consisting of wrappers and disjunct TAMs, and for given pass probabilities per module test, we schedule the tests on each TAM such that the expected test application time is minimized. We describe two heuristic scheduling approaches, one without and one with preemption. Experimental results for the ITC 02 SOC Test Benchmarks demonstrate the effectiveness of our approach, as we achieve up to 97% reduction in the expected test application time, without any modification to the SOC or ATE.
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| 3. |
- Marinissen, Erik Jan, et al.
(author)
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Improved Scan Chain Diagnosis
- 2007
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In: 15th NXP IC Test Symposium,2007.
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Conference paper (other academic/artistic)
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