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- Li, Yi, et al.
(author)
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Photoresistance Switching of Plasmonic Nanopores
- 2015
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In: Nano letters (Print). - : American Chemical Society. - 1530-6984 .- 1530-6992. ; 15:1, s. 776-782
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Journal article (peer-reviewed)abstract
- Fast and reversible modulation of ion flow through nanosized apertures is important for many nanofluidic applications, including sensing and separation systems. Here, we present the first demonstration of a reversible plasmon-controlled nanofluidic valve. We show that plasmonic nanopores (solid-state nanopores integrated with metal nanocavities) can be used as a fluidic switch upon optical excitation. We systematically investigate the effects of laser illumination of single plasmonic nanopores and experimentally demonstrate photoresistance switching where fluidic transport and ion flow are switched on or off. This is manifested as a large (similar to 12 orders of magnitude) increase in the ionic nanopore resistance and an accompanying current rectification upon illumination at high laser powers (tens of milliwatts). At lower laser powers, the resistance decreases monotonically with increasing power, followed by an abrupt transition to high resistances at a certain threshold power. A similar rapid transition, although at a lower threshold power, is observed when the power is instead swept from high to low power. This hysteretic behavior is found to be dependent on the rate of the power sweep. The photoresistance switching effect is attributed to plasmon-induced formation and growth of nanobubbles that reversibly block the ionic current through the nanopore from one side of the membrane. This explanation is corroborated by finite-element simulations of a nanobubble in the nanopore that show the switching and the rectification.
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| 2. |
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| 3. |
- Xiang, Yang, et al.
(author)
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Trap-aware compact modeling and power-performance assessment of III-V tunnel FET
- 2019
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In: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. - 9781538676264
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Conference paper (peer-reviewed)abstract
- We report, for the first time, on a SPICE simulation study of the circuit-level power-performance impact of device traps in a state-of-the-art III-V heterojunction tunnel FET (TFET). First, the individual parasitic effects of junction bulk traps and oxide interface traps are incorporated in a compact model and validated against measurement-calibrated TCAD data, where we propose an analytical formulation for trap-assisted tunneling at the heterojunction and account for the oxide interface charge with a look-up table. Then, the model is used in SPICE simulations on a ring oscillator test bench to predict the impact of traps on logic circuits. It is found that bulk and oxide traps in TFET together cause up to ∼5x iso-frequency energy penalty in the desired low-supply-voltage domain (0.50 V), of which oxide traps dominate at high switching activity while bulk and oxide traps contribute comparably when switching is less active. This study quantitatively suggests that trap reduction is the key to the enablement of the full benefit of TFET.
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