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- Heinle, Ulrich, et al.
(author)
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High Voltage Devices on SOI
- 2001
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In: Presented at the Franco-Swedish Workshop on SOI, March 8-9, Grenoble, France.
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Conference paper (peer-reviewed)
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- Heinle, Ulrich, 1967-
(author)
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Vertical High-Voltage Transistors on Thick Silicon-on-Insulator
- 2003
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Doctoral thesis (other academic/artistic)abstract
- More and more electronic products, like battery chargers and power supplies, as well as applications in telecommunications and automotive electronics are based on System-on-Chip solutions, where signal processing and power devices are integrated on the same chip. The integration of different functional units offers many advantages in terms of reliability, reduced power consumption, weight and space reduction, leading to products with better performance at a hopefully lower price. This thesis focuses on the integration of vertical high-voltage double-diffused MOS transistors (DMOSFETs) on Silicon-on-Insulator (SOI) substrates. MOSFETs possess a number of features which makes them indispensable for Power Integrated Circuits (PICs): high switching speed, high efficiency, and simple drive circuits. SOI substrates combined with trench technology is superior to traditional Junction Isolation (JI) techniques in terms of cross-talk and leakage currents. Vertical DMOS transistors on SOI have been manufactured and characterized, and an analytical model for their on-resistance is presented. A description of self-heating and operation at elevated temperatures is included. Furthermore, the switching dynamics of these components is investigated by means of device simulations with the result that the dissipated power during unclamped inductive switching tests is reduced substantially compared to bulk vertical DMOSFETs. A large number of defects is created in the device layer if the trenches are exposed to high temperatures during processing. A new fabrication process with back-end trench formation is introduced in order to minimize defect generation. In addition, a model for the capacitive coupling between trench-isolated structures is developed.
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- Pinardi, Kuntjoro, 1968, et al.
(author)
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Electrothermal simulations of high-power SOI vertical DMOS transistors with lateral drain contacts under unclamped inductive switching test
- 2004
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In: Solid-State Electronics. - : Elsevier BV. - 0038-1101. ; 48:7, s. 1119-1126
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Journal article (peer-reviewed)abstract
- Electrothermal effects during the unclamped inductive switching (UIS) of silicon-on-insulator (SOI) high power vertical double diffused MOS (VDMOS) transistors have been studied by device simulation. In the UIS test all the energy stored in the inductor during the on state is dumped directly into the device when the device is turned off. This extreme condition during the UIS test will give ratings for the power device and gives a measure for the stability of the device in the breakdown regime. Electrothermal simulations of this device are evaluated under boundary conditions imposed by the UIS circuit. Simulations show that UIS involves a substantial risk of turning the parasitic bipolar transistor (BJT) on. Our measurements of the fabricated SOI VDMOSFET in the static region are in good agreement with the expected impact of the self-heating on the saturation behaviour. The experiments at ambient temperature of 100 °C show that the breakdown voltage decreases as the drain voltage increases. This indicates that the parasitic BJT has been turned on and causes an open-base bipolar transistor breakdown voltage. © 2004 Elsevier Ltd. All rights reserved.
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