| 1. |
- Andric, Stefan, et al.
(author)
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Low-temperature back-end-of-line technology compatible with III-V nanowire MOSFETs
- 2019
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In: Journal of Vacuum Science and Technology B: Nanotechnology and Microelectronics. - : American Vacuum Society. - 2166-2746 .- 2166-2754. ; 37:6
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Journal article (peer-reviewed)abstract
- We present a low-temperature processing scheme for the integration of either lateral or vertical nanowire (NW) transistors with a multilayer back-end-of-line interconnect stack. The nanowire device temperature budget has been addressed, and materials for the interconnect fabrication have been selected accordingly. A benzocyclobutene (BCB) polymer is used as an interlayer dielectric, with interconnect vias formed by reactive ion etching. A study on via etching conditions for multiple interlayer dielectric thicknesses reveals that the sidewall slope can be engineered. An optimal reactive ion etch is identified at 250 mTorr chamber pressure and power of 160 W, using an SF6 to O2 gas mix of 4%. This results in a low via resistance, even for scaled structures. The BCB dielectric etch rate and dielectric-to-soft mask etch selectivity are quantified. Electrical measurements on lateral and vertical III-V NW transistors, before and after the back-end-of-line process, are presented. No performance degradation is observed, only minor differences that are attributed to contact annealing and threshold voltage shift.
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| 2. |
- Andric, Stefan, et al.
(author)
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Performance, Analysis, and Modeling of III-V Vertical Nanowire MOSFETs on Si at Higher Voltages
- 2022
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In: IEEE Transactions on Electron Devices. - 0018-9383. ; 69:6, s. 3055-3055
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Journal article (peer-reviewed)abstract
- Heterostructure engineering in III-V vertical nanowire (VNW) MOSFETs enables tuning of transconductance and breakdown voltage. In this work, an InxGa 1−x As channel with a Ga-composition grading ( x= 1–0.4) in the channel and drain region, combined with field plate engineering, enables breakdown voltage above 2.5 V, while maintaining transconductance of about 1 mS/ μm , in VNW MOSFETs. The field plate consists of a vertically integrated SiO2 layer and a gate contact, which screens the electric field in the drain region, extending the device operating voltage. By scaling the field plate, a transconductance of 2 mS/ μm , alongside the breakdown voltage of 1.5 V, is obtained, demonstrating the benefit of field engineering in the drain. The scalability of the field plate and the gate is measured, showing an ON-resistance increase by 23 Ω⋅μm , and transconductance decrease by 5 μS/μm , per nm field plate length. This behavior is captured in a new and modified virtual source model, where device transmission and drain resistance are altered to capture the field plate scaling effect. The modeling is applied to nanowire (NW) devices with field plate lengths ranging from 5 to 115 nm, capturing accurately essential device performance parameters. Finally, a modified band-to-band (BTB) tunneling approach is used to accurately describe the device behavior above 1.5 V.
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| 3. |
- Berg, Martin, et al.
(author)
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Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si
- 2016
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In: IEEE Electron Device Letters. - 0741-3106. ; 37:8, s. 966-969
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Journal article (peer-reviewed)abstract
- Vertical InAs nanowire transistors are fabricated on Si using a gate-last method, allowing for lithography-based control of the vertical gate length. The best devices combine good ON- and OFF-performance, exhibiting an ON-current of 0.14 mA/μm, and a sub-threshold swing of 90 mV/dec at 190 nm LG. The device with the highest transconductance shows a peak value of 1.6 mS/μm. From RF measurements, the border trap densities are calculated and compared between devices fabricated using the gate-last and gate-first approaches, demonstrating no significant difference in trap densities. The results thus confirm the usefulness of implementing digital etching in thinning down the channel dimensions.
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| 4. |
- Berg, Martin, et al.
(author)
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Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si
- 2016
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In: Technical Digest - International Electron Devices Meeting, IEDM. - 9781467398930 ; 2016-February
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Conference paper (peer-reviewed)abstract
- In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on-and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.
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| 5. |
- Hellenbrand, Markus, et al.
(author)
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Comparison of Low-Frequency Noise in Nanowire and Planar III-V MOSFETs
- 2019
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Conference paper (other academic/artistic)abstract
- We compare III-V nanowire (NW) metal-oxidesemiconductor field-effect transistors (MOSFETs) in a vertical gate-all-around (GAA) as well as a lateral trigate architecture with planar reference MOSFETs and reveal that the NW geometry does not deteriorate the low-frequency noise (LFN) performance. In fact, with gate oxides deposited at the same conditions, the NW structures show potential to achieve better metrics due to slightly lower border trap densities Nbt. The normalized LFN in transistors with a higher number of NW can degrade due to averaging effects between individual nanowires within the same device.
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| 6. |
- Hellenbrand, Markus, et al.
(author)
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Effects of traps in the gate stack on the small-signal RF response of III-V nanowire MOSFETs
- 2020
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In: Solid-State Electronics. - : Elsevier BV. - 0038-1101. ; 171
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Journal article (peer-reviewed)abstract
- We present a detailed study of the effect of gate-oxide-related defects (traps) on the small-signal radio frequency (RF) response of III-V nanowire MOSFETs and find that the effects are clearly identifiable in the measured admittance parameters and in important design parameters such as h21 (forward current gain) and MSG (maximum stable gain). We include the identified effects in a small-signal model alongside results from previous investigations of III-V RF MOSFETs and thus provide a comprehensive physical small-signal RF model for this type of transistor, which accurately describes the measured admittance parameters and gains. We verify the physical basis of the model assumptions by calculating the oxide defect density from the measured admittances.
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| 7. |
- Hellenbrand, Markus, et al.
(author)
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Low-Frequency Noise in III-V Nanowire TFETs and MOSFETs
- 2017
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In: IEEE Electron Device Letters. - 0741-3106.
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Journal article (peer-reviewed)abstract
- We present a detailed analysis of low-frequency noise (LFN) measurements in vertical III-V nanowire tunnel fieldeffect transistors (TFETs), which helps to understand the limiting factors of TFET operation. A comparison with LFN in vertical metal-oxide semiconductor field-effect transistors with the same channel material and gate oxide shows that the LFN in these TFETs is dominated by the gate oxide properties, which allowed us to optimize the TFET tunnel junction without deteriorating the noise performance. By carefully selecting the TFET heterostructure materials, we reduced the inverse subthreshold slope well below 60 mV/decade for a constant LFN level.
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| 8. |
- Hellenbrand, Markus, et al.
(author)
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Low-Frequency Noise in Nanowire and Planar III-V MOSFETs
- 2019
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In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317.
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Journal article (peer-reviewed)abstract
- Nanowire geometries are leading contenders for future low-power transistor design. In this study, low-frequency noise is measured and evaluated in highly scaled III-V nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs) and in planar III-V MOSFETs to investigate to what extent the device geometry affects the noise performance. Number fluctuations are identified as the dominant noise mechanism in both architectures. In order to perform a thorough comparison of the two architectures, a discussion of the underlying noise model is included. We find that the noise performance of the MOSFETs in a nanowire architecture is at least comparable to the planar devices. The input-referred voltage noise in the nanowire devices is superior by at least a factor of four.
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| 9. |
- Kilpi, Olli Pekka, et al.
(author)
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Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs
- 2019
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In: IEEE Journal of the Electron Devices Society. - 2168-6734. ; 7, s. 70-75
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Journal article (peer-reviewed)abstract
- Vertical InAs/InGaAs nanowire MOSFETs are fabricated in a gate-last fabrication process, which allows gate-lengths down to 25 nm and accurate gate-alignment. These devices demonstrate high performance with transconductance of 2.4 mS/μm, high on-current, and off-current below 1 nA/μm. An in-depth analysis of the heterostructure MOSFETs are obtained by systematically varying the gate-length and gate location. Further analysis is done by using virtual source modeling. The injection velocities and transistor metrics are correlated with a quasi-ballistic 1-D MOSFET model. Based on our analysis, the observed performance improvements are related to the optimized gate-length, high injection velocity due to asymmetric scattering, and low access resistance.
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| 10. |
- Kilpi, Olli Pekka, et al.
(author)
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High-Performance Vertical III-V Nanowire MOSFETs on Si with gm> 3 mS/μm
- 2020
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In: IEEE Electron Device Letters. - 0741-3106. ; 41:8, s. 1161-1164
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Journal article (peer-reviewed)abstract
- Vertical III-V nanowire MOSFETs have demonstrated excellent performance including high transconductance and high Ion. One main bottleneck for the vertical MOSFETs is the large access resistance arising from the contacts and ungated regions. We demonstrate a process to reduce the access resistance by combining a gate-last process with ALD gate-metal deposition. The devices demonstrate fully scalable gm down to Lg = 25 nm. These vertical core/shell InAs/InGaAs MOSFETs demonstrate gm = 3.1 mS/μm and Ron = 190 Ωμm. This is the highest gm demonstrated on Si. Transmission line measurement verifies a low contact resistance with RC = 115 Ωμm, demonstrating that most of the MOSFET access resistance is located in the contact regions.
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