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| 2. |
- Balestra, F., et al.
(author)
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NANOSIL network of excellence-silicon-based nanostructures and nanodevices for long-term nanoelectronics applications
- 2008
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In: Materials Science in Semiconductor Processing. - : Elsevier BV. - 1369-8001 .- 1873-4081. ; 11:5-6, s. 148-159
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Journal article (peer-reviewed)abstract
- NANOSIL Network of Excellence [NANOSIL NoE web site < www.nanosil-noe.eu >], funded by the European Commission in the 7th Framework Programme (ICT-FP7, no 216171), aims at European scale integration of the excellent European research laboratories and their capabilities in order to strengthen scientific and technological excellence in the field of nanoelectronic materials and devices for terascale integrated circuits (ICs), and to disseminating the results in a wide scientific and industrial community. NANOSIL is exploring and assessing the science and technological aspects of nanodevices and operational regimes relevant to the n+4 technology node and beyond. It encompasses projects on nanoscale CMOS and beyond-CMOS. Innovative concepts, technologies and device architectures are proposed-with fabrication down to the finest features, and utilising a wide spectrum of advanced deposition and processing capabilities, extensive characterization and very rigorous device modeling. This work is carried out through a network of joint processing, characterization and modeling platforms. This critical interaction strengthens European integration in nanoelectronics and will speed up technological innovation for the nanoelectronics of the next two to three decades.
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| 3. |
- Abermann, S., et al.
(author)
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Comparative study on the impact of TiN and Mo metal gates on MOCVD-grown HfO2 and ZrO2 high-kappa dielectrics for CMOS technology
- 2007
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In: Physics of Semiconductors, Pts A and B. - : AIP. - 9780735403970 ; , s. 293-294
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Conference paper (peer-reviewed)abstract
- We compare metal oxide semiconductor capacitors, investigating Titanium-Nitride and Molybdenum as gate materials, as well as metal organic chemical vapor deposited ZrO2 and HfO2 as high-kappa dielectrics, respectively. The impact of different annealing steps on the electrical characteristics of the various gate stacks is a further issue. The positive effect of post metallization annealing in forming gas atmosphere as well as observed mid-gap pinning of TiN and Mo metal gates is presented.
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| 4. |
- Abermann, S., et al.
(author)
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Impact of Al-, Ni-, TiN-, and Mo-metal gates on MOCVD-grown HfO2 and ZrO2 high-k dielectrics
- 2007
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In: Microelectronics and reliability. - : Elsevier BV. - 0026-2714 .- 1872-941X. ; 47:4-5, s. 536-539
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Journal article (peer-reviewed)abstract
- In this work we compare the impacts of nickel (Ni), titanium-nitride (TiN), molybdenum (Mo), and aluminium (Al), gates on MOS capacitors incorporating HfO2- or ZrO2-dielectrics. The primary focus lies on interface trapping, oxide charging, and thermodynamical stability during different annealing steps of these gate stacks. Whereas Ni, Mo, and especially TIN are investigated as most promising candidates for future CMOS devices, Al acted as reference gate material to benchmark the parameters. Post-metallization annealing of both, TiN- and Mo-stacks, resulted in very promising electrical characteristics. However, gate stacks annealed at temperatures of 800 degrees C or 950 degrees C show thermodynamic instability and related undesirable high leakage currents.
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| 5. |
- Abermann, S., et al.
(author)
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Processing and evaluation of metal gate/high-k/Si capacitors incorporating Al, Ni, TiN, and Mo as metal gate, and ZrO2 and HfO2 as high-k dielectric
- 2007
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In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 84:5-8, s. 1635-1638
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Journal article (peer-reviewed)abstract
- We evaluate various metal gate/high-k/Si capacitors by their resulting electrical characteristics. Therefore, we process MOS gate stacks incorporating aluminium (Al), nickel (Ni), titanium-nitride (TiN), and molybdenum (Mo) as the gate material, and metal organic chemical vapour deposited (MOCVD) ZrO2 and HfO2 as the gate dielectric, respectively. The influence of the processing sequence - especially of the thermal annealing treatment - on the electrical characteristics of the various gate stacks is being investigated. Whereas post metallization annealing in forming gas atmosphere improves capacitance-voltage behaviour (due to reduced interface-, and oxide charge density), current-voltage characteristics degrade due to a higher leakage current after thermal treatment at higher temperatures. The Flatband-voltage values for the TiN-, Mo-, and Ni-capacitors indicate mid-gap pinning of the metal gates, however, Ni seems to be thermally unstable on ZrO2, at least within the process scheme we applied.
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| 6. |
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| 7. |
- Abermann, S., et al.
(author)
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Processing and evaluation of metal gate/high-kappa/Si capacitors incorporating Al, Ni, TiN, and Mo as metal gate, and ZrO2 and HfO2 as high-kappa dielectric
- 2007
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In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 84:5-8, s. 1635-1638
-
Journal article (peer-reviewed)abstract
- We evaluate various metal gate/high-K/Si capacitors by their resulting electrical characteristics. Therefore, we process MOS gate stacks incorporating aluminium (Al), nickel (Ni), titanium-nitride (TiN), and molybdenum (Mo) as the gate material, and metal organic chemical vapour deposited (MOCVD) ZrO2 and HfO2 as the gate dielectric, respectively. The influence of the processing sequence - especially of the thermal annealing treatment - on the electrical characteristics of the various gate stacks is being investigated. Whereas post metallization annealing in forming gas atmosphere improves capacitance-voltage behaviour (due to reduced interface-, and oxide charge density), current-voltage characteristics degrade due to a higher leakage current after thermal treatment at higher temperatures. The Flatband-voltage values for the TiN-, Mo-, and Ni-capacitors indicate mid-gap pinning of the metal gates, however, Ni seems to be thermally unstable on ZrO2, at least within the process scheme we applied.
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| 8. |
- Benetti, M., et al.
(author)
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POLYSILICON MESOSCOPIC WIRES COATED BY Pd AS H(2) SENSORS
- 2009
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In: PROCEEDINGS OF THE 13TH ITALIAN CONFERENCE ON SENSORS AND MICROSYSTEMS. - SINGAPORE : WORLD SCIENTIFIC PUBL CO PTE LTD. ; , s. 161-165
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Conference paper (peer-reviewed)abstract
- In this work a novel monocrystalline silicon nanowires array has been investigated and presented as hydrogen sensor, designed and fabricated by employing high resolution microfabrication techniques and featuring a high surface/volume ratio. The nanowires arrays makes up the channel of a MOS system, palladium-silicon dioxide-silicon. Several devices have been fabricated by using a SOI (Silicon On Insulator) substrate, Source and Drain have been geometrically patterned by optical lithography and Boron p-doped. Electron Beam Litography (EBL) defined the MOS channel made up of a nanowires array of different length and width in different transistors. The pads of Source and Drain have been manufactured with an aluminium film deposition. The Gate has been fabricated with a grown silicon oxide layer (17.4 nm) and Palladium has been used as gate contact. Polarizing and exposing the device to H(2)/N(2) cycles at different concentrations some preliminary measurements have been successfully conducted.
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| 9. |
- Czernohorsky, M., et al.
(author)
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Stability of crystalline Gd(2)O(3) thin films on silicon during rapid thermal annealing
- 2008
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In: Semiconductor Science and Technology. - : IOP Publishing. - 0268-1242 .- 1361-6641. ; 23:3, s. 035010-
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Journal article (peer-reviewed)abstract
- We investigate the impact of rapid thermal anneals on structural and electrical properties of crystalline Gd(2)O(3) layers grown on Si with different orientations. Due to additional oxygen from the annealing ambient, a structureless two-layer stack ( silicon-oxide-like and silicate-like) between the silicon and the crystalline oxide will be formed. The degradation of layers can be significantly reduced by sealing the layer with a-Si prior to annealing. For the capped layers, the effective capacitance equivalent thickness increases only slightly even after a 1000 degrees C anneal.
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| 10. |
- Gottlob, H. D. B., et al.
(author)
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0.86-nm CET gate stacks with epitaxial Gd2O3 high-k dielectrics and FUSINiSi metal electrodes
- 2006
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In: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 27:10, s. 814-816
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Journal article (peer-reviewed)abstract
- In this letter, ultrathin gadolinium oxide (Gd2O3) high-kappa gate dielectrics with complementary-metal-oxide-semiconductor (CMOS)-compatible fully silicided nickel-silicide metal gate electrodes are reported for the first time. MOS capacitors with a Gd2O3 thickness of 3.1 nm yield a capacitance equivalent oxide thickness of CET = 0.86 nm. The extracted dielectric constant is kappa =-13-14. Leakage currents and equivalent oxide thicknesses of this novel gate stack meet the International Technology Roadmap for Semiconductors targets for the near term schedule and beyond.
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