| 1. |
- Marranghello, Felipe, et al.
(författare)
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Four-level forms for memristive material implication logic
- 2019
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Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : Institute of Electrical and Electronics Engineers Inc.. - 1063-8210 .- 1557-9999. ; 27:5, s. 1228-1232
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Tidskriftsartikel (refereegranskat)abstract
- This brief proposes the use of four-level forms in the memristive material implication (M-IMP) logic. M-IMP is a promising approach to perform stateful logic in memristive nonvolatile memories. In such a design technique, a given Boolean function is evaluated as a sequence of instructions, making logic synthesis methods necessary to attain the shortest sequence. In comparison to previous work, experimental results have shown an average reduction of 40% when evaluating the tradeoff between the numbers of instructions and memristive devices.
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| 2. |
- Marranghello, Felipe, et al.
(författare)
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Threshold Physical Unclonable Functions
- 2019
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Ingår i: 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL). - : IEEE conference proceedings. ; , s. 55-60
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Konferensbidrag (refereegranskat)abstract
- Physical Unclonable Functions (PUFs) have been proposed as a tamper-resistant alternative to the traditional methods for secret key generation and challenge-response authentication. Although many different types of PUFs have been presented, the search for more efficient, reliable and secure PUFdesigns continues. In this paper, we introduce a new class of PUFs, called threshold PUFs. We show that, in principle, any n-input threshold logic gate can be used as a base for building an n-input PUF. This opens up the possibility of using a rich body of knowledge on threshold logic implementations for designing PUFs. As a proof of concept, we implement and evaluate binary and ternary PUFs based on recently proposed threshold logic flip-flops.
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| 3. |
- Neto, W. L., et al.
(författare)
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Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation
- 2018
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Ingår i: 31st Symposium on Integrated Circuits and Systems Design, SBCCI 2018. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781538674314
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Konferensbidrag (refereegranskat)abstract
- Logic synthesis is a crucial step in digital integrated circuit design. There are methods for exact synthesis of two-level design able to handle very large circuits, with hundred of inputs, although of limited usefulness in VLSI circuit and system design. On the other hand, exact multi-level synthesis is a quite complex task, where the majority of algorithms are heuristic. To evaluate and validate new methods, benchmarks are of great importance. In particular, exact benchmarks unlock the possibility to evaluate the effectiveness of synthesis algorithm with respect to the optimal solution. This work proposes a novel method to generate exact multi-level circuits based on reversible logic. The proposed approach is able to build exact benchmark circuits with around 40 millions nodes in short time, acting as the identity function $f(x)=x$. It means, the most compact circuit corresponds to only wires, without any logic gate instantiation. The proposed work is complementary to other circuit generation approaches, being easily combined to explore particular characteristics of related benchmarks.
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| 4. |
- Yu, Yang, et al.
(författare)
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One-sided countermeasures for side-channel attacks can backfire
- 2018
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Ingår i: WiSec 2018 - Proceedings of the 11th ACM Conference on Security and Privacy in Wireless and Mobile Networks. - New York, NY, USA : Association for Computing Machinery, Inc. - 9781450357319 ; , s. 299-301
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Konferensbidrag (refereegranskat)abstract
- Side-channel attacks are currently one of the most powerful attacks against implementations of cryptographic algorithms. They exploit the correlation between the physical measurements (power consumption, electromagnetic emissions, timing) taken at different points during the computation and the secret key. Some of the existing countermeasures offer a protection against one specific type of side channel only. We show that it can be a bad practice which can make exploitation of other side-channels easier. First, we perform a power analysis attack on an FPGA implementation of the Advanced Encryption Standard (AES) which is not protected against side-channel attacks and estimate the number of power traces required to extract its secret key. Then, we repeat the attack on AES implementations which are protected against fault injections by hardware redundancy and show that they can be broken with three times less power traces than the unprotected AES. We also demonstrate that the problem cannot be solved by complementing the duplicated module, as previously proposed. Our results show that there is a need for increasing knowledge about side-channel attacks and designing stronger countermeasures.
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