| 1. |
- Yin, X., et al.
(author)
-
Vertical Sandwich Gate-All-Around Field-Effect Transistors with Self-Aligned High-k Metal Gates and Small Effective-Gate-Length Variation
- 2020
-
In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers Inc.. - 0741-3106 .- 1558-0563. ; 41:1, s. 8-11
-
Journal article (peer-reviewed)abstract
- A new type of vertical nanowire (NW)/nanosheet (NS) field-effect transistors (FETs), termed vertical sandwich gate-all-around (GAA) FETs (VSAFETs), is presented in this work. Moreover, an integration flow that is compatible with processes used in the mainstream industry is proposed for the VSAFETs. Si/SiGe epitaxy, isotropic quasi-atomic-layer etching (qALE), and gate replacement were used to fabricate pVSAFETs for the first time. Vertical GAA FETs with self-aligned high-k metal gates and a small effective-gate-length variation were obtained. Isotropic qALE, including Si-selective etching of SiGe, was developed to control the diameter/thickness of the NW/NS channels. NWs with a diameter of 10 nm and NSs with a thickness of 20 nm were successfully fabricated, and good device characteristics were obtained. Finally, the device performance was investigated and is discussed in this work. © 2019 IEEE.
|
|
| 2. |
- Li, J., et al.
(author)
-
Study of silicon nitride inner spacer formation in process of gate-all-around nano-transistors
- 2020
-
In: Nanomaterials. - : MDPI AG. - 2079-4991. ; 10:4
-
Journal article (peer-reviewed)abstract
- Stacked SiGe/Si structures are widely used as the units for gate-all-around nanowire transistors (GAA NWTs) which are a promising candidate beyond fin field effective transistors (FinFETs) technologies in near future. These structures deal with a several challenges brought by the shrinking of device dimensions. The preparation of inner spacers is one of the most critical processes for GAA nano-scale transistors. This study focuses on two key processes: Inner spacer film conformal deposition and accurate etching. The results show that low pressure chemical vapor deposition (LPCVD) silicon nitride has a good film filling effect; a precise and controllable silicon nitride inner spacer structure is prepared by using an inductively coupled plasma (ICP) tool and a new gas mixtures of CH2F2/CH4/O2/Ar. Silicon nitride inner spacer etch has a high etch selectivity ratio, exceeding 100:1 to Si and more than 30:1 to SiO2. High anisotropy with an excellent vertical/lateral etch ratio exceeding 80:1 is successfully demonstrated. It also provides a solution to the key process challenges of nano-transistors beyond 5 nm node. © 2020 by the authors. Licensee MDPI, Basel, Switzerland.
|
|
| 3. |
- Qin, C., et al.
(author)
-
Study of sigma-shaped source/drain recesses for embedded-SiGe pMOSFETs
- 2017
-
In: Microelectronic Engineering. - : Elsevier. - 0167-9317 .- 1873-5568. ; 181, s. 22-28
-
Journal article (peer-reviewed)abstract
- In this paper, the manufacturing process and formation mechanism study of sigma-shaped source/drain (S/D) recess in 28 nm node pMOSFETs and beyond have been presented. The mechanism of forming sigma-shaped recesses included a detailed analysis how to apply the dry and wet etching to shape the recess in a controlled way. The key factors in etching parameters were identified and optimized. Simulations of strain distributions in the channel region of the devices with selectively grown Si0.65Ge0.35 on different S/D recess shapes were carried out and the results were used as feedback to find out a trade-off between maximum strain in the channel region of the transistors and low short channel effect. Finally, guidelines for designing the shape of recess and for tuning the etching parameters for high mobility transistors have been proposed.
|
|
| 4. |
- Li, J., et al.
(author)
-
Study of selective isotropic etching Si1−xGex in process of nanowire transistors
- 2020
-
In: Journal of materials science. Materials in electronics. - : Springer Science and Business Media LLC. - 0957-4522 .- 1573-482X. ; 31:1, s. 134-143
-
Journal article (peer-reviewed)abstract
- On approach towards the end of technology roadmap, a revolutionary approach towards the nanowire transistors is favorable due to the full control of carrier transport. The transistor design moves toward vertically or laterally stacked Gate-All-Around (GAA) where Si or SiGe can be used as channel material. This study presents a novel isotropic inductively coupled plasma (ICP) dry etching of Si1−xGex (0.10 ≤ x ≤ 0.28) in SiGe/Si multilayer structures (MLSs) with high selectivity to Si, SiO2, Si3N4 and SiON which can be applied in advanced 3D transistors and Micro-Electro-Mechanical System (MEMS) in future. The profile of SiGe etching for different thicknesses, compositions and locations in MLSs using dry or wet etch have been studied. A special care has been spent for layer quality of Si, strain relaxation of SiGe layers as well as residual contamination during the etching. In difference with dry etching methods (downstream remote plasma), the conventional ICP source in situ is used where CF4/O2/He gas mixture was used as the etching gas to obtain higher selectivity. Based on the reliability of ICP technique a range of etching rate 25–50 nm/min can be obtained for accurate isotropic etching of Si1−xGex, to form cavity in advanced 3D transistor processes in future.
|
|
| 5. |
|
|
| 6. |
- Li, C., et al.
(author)
-
Growth and Selective Etch of Phosphorus-Doped Silicon/Silicon–Germanium Multilayers Structures for Vertical Transistors Application
- 2020
-
In: Nanoscale Research Letters. - : Springer. - 1931-7573 .- 1556-276X. ; 15:1
-
Journal article (peer-reviewed)abstract
- Vertical gate-all-around field-effect transistors (vGAAFETs) are considered as the potential candidates to replace FinFETs for advanced integrated circuit manufacturing technology at/beyond 3-nm technology node. A multilayer (ML) of Si/SiGe/Si is commonly grown and processed to form vertical transistors. In this work, the P-incorporation in Si/SiGe/Si and vertical etching of these MLs followed by selective etching SiGe in lateral direction to form structures for vGAAFET have been studied. Several strategies were proposed for the epitaxy such as hydrogen purging to deplete the access of P atoms on Si surface, and/or inserting a Si or Si0.93Ge0.07 spacers on both sides of P-doped Si layers, and substituting SiH4 by SiH2Cl2 (DCS). Experimental results showed that the segregation and auto-doping could also be relieved by adding 7% Ge to P-doped Si. The structure had good lattice quality and almost had no strain relaxation. The selective etching between P-doped Si (or P-doped Si0.93Ge0.07) and SiGe was also discussed by using wet and dry etching. The performance and selectivity of different etching methods were also compared. This paper provides knowledge of how to deal with the challenges or difficulties of epitaxy and etching of n-type layers in vertical GAAFETs structure. © 2020, The Author(s).
|
|
| 7. |
- Pavlov, S. G., et al.
(author)
-
Terahertz emission from phosphor centers in SiGe and SiGe/Si semiconductors
- 2008
-
Conference paper (peer-reviewed)abstract
- Terahertz-range photoluminescence from silicon-germanium crystals and superlattices doped by phosphor has been studied under optical excitation by radiation from a mid-infrared CO2 laser at low temperature. SiGe crystals with a Ge content between 0.9 and 6.5%, doped by phosphor with a concentration optimal for silicon laser operation, do not exhibit terahertz gain. On the contrary, terahertz-range gain of ∼ 2.3-3.2 cm-1 has been observed for donor-related optical transitions in Si/SiGe strained superlattices at pump intensities above 100 kW/cm2.
|
|
| 8. |
- Qin, C., et al.
(author)
-
A novel method for source/drain ion implantation for 20 nm FinFETs and beyond
- 2020
-
In: Journal of materials science. Materials in electronics. - : Springer Science and Business Media LLC. - 0957-4522 .- 1573-482X. ; 31, s. 98-104
-
Journal article (peer-reviewed)abstract
- This paper presents a method to improve source/drain extension (SDE) ion implantation (I/I) process for sub-20 nm node FinFETs with no extra step in transistor process. Traditionally, SDE I/I process needs a large implant tilt angle and a high dose to obtain a heavy and conformal doping. However, this process leads to implantation shadow effects and Si-fin amorphization. These drawbacks can be removed in our new approach when SDE I/I is modified and moved after S/D epitaxy process (SDE I/I-last). Because of the facet planes of the SiGe layer, the ions are allowed to be implanted with small tilt. This is helpful to avoid shadow effects of implantation and to keep the low defect density in the S/D. As a result, the external resistance (R EXTRNL ) is not high and the strain relaxation is minor in S/D epitaxy layer. Finally, p-type FinFETs with 25 nm gate length with SDE I/I-last are fabricated. These new FinFETs demonstrate ~ 50% on-state current (I ON ) improvement compared to those transistors fabricated by traditional method.
|
|
| 9. |
- Radamson, Henry H., et al.
(author)
-
Optimization of Selective Growth of SiGe for Source/Drain in 14nm and beyond Nodes FinFETs
- 2017
-
In: International Journal of High Speed Electronics and Systems. - : World Scientific Publishing Co. Pte Ltd. - 0129-1564. ; 26:1-2
-
Journal article (peer-reviewed)abstract
- In this work, optimization of selective epitaxy growth (SEG) of SiGe layers on source/drain (S/D) areas in 14nm node FinFETs with high-k & metal gate has been presented. The Ge content in epilayers was in range of 30%-40% with boron concentration of 1-3 × 1020 cm-3. The strain distribution in the transistor structure due to SiGe as stressor material in S/D was simulated and these results were used as feedback to design the layer profile. The epitaxy parameters were optimized to improve the layer quality and strain amount of SiGe layers. The in-situ cleaning of Si fins was crucial to grow high quality layers and a series of experiments were performed in range of 760-825 °C. The results demonstrated that the thermal budget has to be within 780-800 °C in order to remove the native oxide but also to avoid any harm to the shape of Si fins. The Ge content in SiGe layers was directly determined from the misfit parameters obtained from reciprocal space mappings using synchrotron radiation. Atomic layer deposition (ALD) technique was used to deposit HfO2 as high-k dielectric and B-doped W layer as metal gate to fill the gate trench. This type of ALD metal gate has decent growth rate, low resistivity and excellent capability to fill the gate trench with high aspect-ratio. Finally, the electrical characteristics of fabricated FinFETs were demonstrated and discussed.
|
|
| 10. |
- Radamson, Henry H., et al.
(author)
-
Optimization of Selective Growth of SiGe for Source/Drain in 14nm and Beyond Nodes FinFETs
- 2017
-
In: Scaling and Integration of High-Speed Electronics and Optomechanical Systems. - : World Scientific Pub Co Pte Ltd. ; , s. 99-107
-
Book chapter (other academic/artistic)abstract
- In this work, optimization of selective epitaxy growth (SEG) of SiGe layers on source/drain (S/D) areas in 14nm node FinFETs with high-k and metal gate has been presented. The Ge content in epilayers was in range of 30%-40% with boron concentration of 1-3 × 1020 cm-3. The strain distribution in the transistor structure due to SiGe as stressor material in S/D was simulated and these results were used as feedback to design the layer profile. The epitaxy parameters were optimized to improve the layer quality and strain amount of SiGe layers. The in-situ cleaning of Si fins was crucial to grow high quality layers and a series of experiments were performed in range of 760-825 °C. The results demonstrated that the thermal budget has to be within 780-800 °C in order to remove the native oxide but also to avoid any harm to the shape of Si fins. The Ge content in SiGe layers was directly determined from the misfit parameters obtained from reciprocal space mappings using synchrotron radiation. Atomic layer deposition (ALD) technique was used to deposit HfO2 as high-k dielectric and B-doped W layer as metal gate to fill the gate trench. This type of ALD metal gate has decent growth rate, low resistivity and excellent capability to fill the gate trench with high aspect-ratio. Finally, the electrical characteristics of fabricated FinFETs were demonstrated and discussed.
|
|
