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Träfflista för sökning "WFRF:(Raskin Jean Pierre) "

Search: WFRF:(Raskin Jean Pierre)

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1.
  • Esfeh, Babak Kazemi, et al. (author)
  • Low-cost wideband double-layer microstrip coupled-line directional coupler with high directivity
  • 2014
  • In: Microwave and optical technology letters (Print). - : Wiley. - 0895-2477 .- 1098-2760. ; 56:7, s. 1570-1575
  • Journal article (peer-reviewed)abstract
    • In this article, a low-cost double-layer microstrip structure with a gap space between the two substrate layers is used to develop a microstrip coupled-line directional coupler with high directivity. The proposed design shows a high directivity (more than 20 dB) over a wide frequency bandwidth (more than 2 GHz). The double-layer directional coupler, designed on FR4 substrate material at 2.4 GHz provides more than 30 dB isolation. The simulation and measurement results are in good agreement. By applying a simple and low-cost fabrication process and design, the directivity of the directional coupler is enhanced by more than 10 dB compared with a microstrip structure. 
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  • Lotfi, Sara (author)
  • Design and Characterization of RF-LDMOS Transistors and Si-on-SiC Hybrid Substrates
  • 2014
  • Doctoral thesis (other academic/artistic)abstract
    • With increasing amount of user data and applications in wireless communication technology, demands are growing on performance and fabrication costs. One way to decrease cost is to integrate the building blocks in an RF system where digital blocks and high power amplifiers then are combined on one chip. This thesis presents LDMOS transistors integrated in a 65 nm CMOS process without adding extra process steps or masks. High power performance of the LDMOS is demonstrated for an integrated WLAN-PA design at 2.45 GHz with 32.8 dBm output power and measurements also showed that high output power is achievable at 5.8 GHz. For the first time, this kind of device is moreover demonstrated at X-band with over 300 mW/mm output power, targeting communication and radar systems at 8 GHz. As SOI is increasing in popularity due to better device performance and RF benefits, the buried oxide can cause thermal problems, especially for high power devices. To deal with self-heating effects and decrease the RF substrate losses further, this thesis presents a hybrid substrate consisting of silicon on top of polycrystalline silicon carbide (Si-on-poly-SiC). This hybrid substrate utilizes the high thermal conductivity of poly-SiC to reduce device self-heating and the semi-insulating properties to reduce RF losses. Hybrid substrates were successfully fabricated for the first time in 150 mm wafer size by wafer bonding and evaluation was performed in terms of both electrical and thermal measurements and compared to a SOI reference. Successful LDMOS transistors were fabricated for the first time on this type of hybrid substrate where no degradation in electrical performance was seen comparing the LDMOS to identical transistors on the SOI reference. Measurements on calibrated resistors showed that the thermal conductivity was 2.5 times better for the hybrid substrate compared to the SOI substrate. Moreover, RF performance of the hybrid substrate was investigated and the semi-insulating property of poly-SiC showed to be beneficial in achieving a high equivalent substrate parallel resistance and thereby low substrate losses. In a transistor this would be equal to better efficiency and output power. In terms of integration, the hybrid substrate also opens up the possibility of heterogeneous integration where silicon devices and GaN devices can be fabricated on the same chip.
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  • Passi, V., et al. (author)
  • Note: Fast and reliable fracture strain extraction technique applied to silicon at nanometer scale
  • 2011
  • In: Review of Scientific Instruments. - : AIP Publishing. - 1089-7623 .- 0034-6748. ; 82:11, s. art. no 116106-
  • Journal article (peer-reviewed)abstract
    • Simple fabrication process and extraction procedure to determine the fracture strain of monocrystalline silicon are demonstrated. Nanowires/nanoribbons in silicon are fabricated and subjected to uniaxial tensile stress along the complete length of the beams. Large strains up to 5% are measured for nanowires presenting a cross section of 50 nm × 50 nm and a length of 2.5 μm. An increase in fracture strain for silicon nanowires (NWs) with the downscaling of their volume is observed, highlighting the reduction of the defects probability as volume is decreased.
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6.
  • Passi, Vikram, et al. (author)
  • Suspended silicon-on-insulator nanowires for the fabrication of quadruple gate mosfets
  • 2007
  • In: Nanoscaled Semiconductor-on-Insulator Structures and Devices. - Dordrecht : Springer Netherlands. - 9781402063787 ; , s. 89-94
  • Conference paper (peer-reviewed)abstract
    • Scaling of MOSFET physical dimensions is approaching the OF nanoscale regime, which causes increase of short-channel effects such that the electrical performance of classical MOSFET structure is becoming seriously degraded. The limits of silicon scaling have been the major challenge for technologists for the past years. With the 90 nm generation in production and despite many roadblocks, the latest International Roadmap for Semiconductors 2005 expects that CMOS can be scaled down to 16 nm, by introducing new transistor architectures and materials. In this paper, we propose fabrication of a non-classical device architecture namely the "Quadruple-Gate MOSFET" which is based on definition of narrow, suspended silicon fins defined by electron-beam lithography into the top-silicon film of a Silicon-on-Insulator (SOI) wafer.
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  • Result 1-6 of 6

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