SwePub - search: WFRF:(Roshanisefat Shervin)

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1.	Rezaei, Seyyed Hossein Seyyedaghaei, et al. (author) A Three-Dimensional Networks-on-Chip Architecture with Dynamic Buffer Sharing 2016 In: 2016 24TH EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, AND NETWORK-BASED PROCESSING (PDP). - 9781467387767 ; , s. 771-776 Conference paper (peer-reviewed)abstract 3D integration is a practical solution for overcoming the failure of Dennard scaling in future technology generations. This emerging technology stacks several die slices on top of each other on a single chip in order to provide higher-bandwidth and lower-latency than a 2D design due to extremely shorter inter-layer distances in the third dimension and. In this paper, we leverage the low latency vertical links to address buffer management, one of the most important design and management issues in Network-on-Chip(NoC). To this end, we present VerBuS, an architecture for 3D routers with Vertical BUffer Sharing capability enabled by ultra-low latency vertical links of a 3D chip. VerBuS can share virtual channels (VC) between vertically stacked routers. This way, the buffering capacity of a highly loaded router is increased by using idle VCs of vertically adjacent routers. Experimental results show up to 20% improvement in NoC performance metrics over state-of-the-art 3D router designs.

Rezaei, Seyyed Hossein Seyyedaghaei, et al. (author)
A Three-Dimensional Networks-on-Chip Architecture with Dynamic Buffer Sharing
2016
In: 2016 24TH EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, AND NETWORK-BASED PROCESSING (PDP). - 9781467387767 ; , s. 771-776
Conference paper (peer-reviewed)abstract
- 3D integration is a practical solution for overcoming the failure of Dennard scaling in future technology generations. This emerging technology stacks several die slices on top of each other on a single chip in order to provide higher-bandwidth and lower-latency than a 2D design due to extremely shorter inter-layer distances in the third dimension and. In this paper, we leverage the low latency vertical links to address buffer management, one of the most important design and management issues in Network-on-Chip(NoC). To this end, we present VerBuS, an architecture for 3D routers with Vertical BUffer Sharing capability enabled by ultra-low latency vertical links of a 3D chip. VerBuS can share virtual channels (VC) between vertically stacked routers. This way, the buffering capacity of a highly loaded router is increased by using idle VCs of vertically adjacent routers. Experimental results show up to 20% improvement in NoC performance metrics over state-of-the-art 3D router designs.

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