| 1. |
- Asbeck, Peter M., et al.
(author)
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Power Amplifiers for mm-Wave 5G Applications: Technology Comparisons and CMOS-SOI Demonstration Circuits
- 2019
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In: IEEE Transactions on Microwave Theory and Techniques. - 0018-9480 .- 1557-9670. ; 67:7, s. 3099-3109
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Journal article (peer-reviewed)abstract
- A review is presented of key power amplifier (PA) performance requirements for millimeter-wave 5G systems, along with a comparison of the potential of different semiconductor technologies for meeting those requirements. Output power, efficiency, and linearity considerations are highlighted, and related to semiconductor material characteristics. Prototype 5G PAs based on silicon technologies are then reviewed, with primary emphasis on CMOS-SOI. Stacked FET PAs based on nMOS and pMOS for 28-GHz operation are presented, along with outphasing and Doherty amplifiers. Peak power-added efficiency (PAE) up to 46% is demonstrated for a two-stack pMOS amplifier with saturation power (Psat) above 19 dBm. PAE at 6 dB backoff above 27% is shown for an nMOS Doherty PA with 22-dBm Psat. Operation with 64QAM OFDM modulation signals at 800-MHz bandwidth is reported, with up to 13-dBm output power and more than 17% PAE, without the use of digital predistortion. Future challenges for PA development are discussed.
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| 2. |
- Rostomyan, Narek, et al.
(author)
-
28 GHz Doherty Power Amplifier in CMOS SOI With 28% Back-Off PAE
- 2018
-
In: IEEE Microwave and Wireless Components Letters. - 1558-1764 .- 1531-1309. ; 28:5, s. 446-448
-
Journal article (peer-reviewed)abstract
- A single-stage, symmetric Doherty power amplifier (PA) in 45 nm CMOS silicon on insulator at 28 GHz is presented. The PA achieves a saturated output power of 22.4 dBm, a peak power added efficiency (PAE) of 40%, and a 6 dB backoff PAE of 28%. High efficiency is attained due to low combiner losses of 0.5 dB, obtained using a recently developed combiner synthesis technique. A compact modeling approach for parasitic-extracted PA transistors is presented, which considerably reduced simulation time. The PA is based on two-stack power devices and occupies overall chip area of only 0.63 mm(2), including pads.
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| 3. |
- ÖZEN, MUSTAFA, 1984, et al.
(author)
-
Efficient Millimeter Wave Doherty PA Design Based on a Low-Loss Combiner Synthesis Technique
- 2017
-
In: IEEE Microwave and Wireless Components Letters. - 1558-1764 .- 1531-1309. ; 27:12, s. 1143-1145
-
Journal article (peer-reviewed)abstract
- We report on a record-efficient 30-GHz 21-dBm differential Doherty PA designed in a 130-nm SiGe process. The output network is designed using a recently developed combiner synthesis technique. This technique enables impedance inversion and parasitic compensation to be integrated in one compact network. As a result, the combiner loss is reduced with 0.3-0.5 dB compared with a conventional Doherty combiner. The measured collector and power-added efficiencies at 6-dB back-off level are 30% and 24.3%, respectively, which further validates the advantages of the design technique.
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