| 1. |
- Alvandpour, Atila, 1960-, et al.
(author)
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A sub-130-nm conditional keeper technique
- 2002
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In: IEEE Journal of Solid-State Circuits. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9200 .- 1558-173X. ; 37:5, s. 633-638
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Journal article (peer-reviewed)abstract
- Increasing leakage currents combined with reduced noise margins significantly degrade the robustness of wide dynamic circuits. In this paper, we describe two conditional keeper topologies for improving the robustness of sub-130-nm wide dynamic circuits. They are applicable in normal mode of operation as well as during burn-in test. A large fraction of the keepers is activated conditionally, allowing the use of strong keepers with leaky precharged circuits without significant impact on performance of the circuits. Compared to conventional techniques, up to 28% higher performance has been observed for wide dynamic gates in a 130-nm technology. In addition, the proposed burn-in keeper results in 64% active area reduction
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| 2. |
- Krishnamurthy, R.K., et al.
(author)
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A 130-nm 6-GHz 256x32 bit leakage-tolerant register file
- 2002
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In: IEEE Journal of Solid-State Circuits. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9200 .- 1558-173X. ; 37:5, s. 624-632
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Journal article (peer-reviewed)abstract
- Describes a 256-word × 32-bit 4-read, 4-write ported register file for 6-GHz operation in 1.2-V 130-nm technology. The local bitline uses a pseudostatic technique for aggressive bitline active leakage reduction/tolerance to enable 16 bitcells/bitline, low-Vt usage, and 50% keeper downsizing. Gate-source underdrive of -V cc on read-select transistors is established without additional supply/bias voltages or gate-oxide overstress. 8% faster read performance and 36% higher dc noise robustness is achieved compared to dual-Vt bitline scheme optimized for high performance. Device-level measurements in the 130-nm technology show 703× bitline active leakage reduction, enabling continued Vt scaling and robust bitline scalability beyond 130-nm generation. Sustained performance and robustness benefit of the pseudostatic technique against conventional dynamic bitline with keeper-upsizing is also presented
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| 6. |
- Alvandpour, Atila, 1960-, et al.
(author)
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Integrated circuits bus architecture including a full-swing, clocked, commongate receiver for fast on-chip signal transmission
- 2002
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Patent (pop. science, debate, etc.)abstract
- An integrated circuit (IC) bus architecture is disclosed. The bus architecture includes a receiver for fast on-chip signal transmission. The receiver includes a first gate device having one terminal connected to a voltage source and a gate terminal connectable to receive a sense signal. A second gate device includes one terminal connected to another terminal of the first gate device, a gate terminal connectable to receive the sense signal and another terminal serving as an input terminal of the receiver and connectable to an interconnect bus to receive input signals from other components on the IC chip. The receiver also includes a third gate device having one terminal connected to a voltage source and another terminal serving as an output terminal of the receiver and connected to the other terminal of the first gate device. The receiver further includes an inverter having an input terminal connected to the output of the receiver and having an output terminal connected to a gate terminal of the third gate device. The input of the receiver is capable of being pre-discharged to a low signal and the output of the receiver is capable of being pre-charged to a high signal for substantially instantaneous transmission of input signals received by the receiver.
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| 7. |
- Alvandpour, Atila, 1960-, et al.
(author)
-
Leakage-tolerant circuit and method for large register files
- 2002
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Patent (pop. science, debate, etc.)abstract
- A novel circuit technique for reducing leakage currents through the read-path of large register files in which a negative gate-source voltage is forced on a critical pass transistor between a cell read transistor and a local bitline such that when the cell is in a first state, the leakage current from a dynamic node of the cell read transistor is reduced. The reduced leakage current increases the robustness and performance of the read operation.
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