| 1. |
- Andersson, Kristoffer, 1976, et al.
(author)
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Fabrication and characterization of field-plated buried-gate SiC MESFETs
- 2006
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In: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 27:7, s. 573-575
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Journal article (peer-reviewed)abstract
- Silicon carbide (SiC) MESFETs were fabricated using a standard SiC MESFET structure with the application of the "buried-channel" and field-plate (FP) techniques in the process. FPs combined with a buried-gate are shown to be favorable concerning output power density and power-added efficiency (PAE), due to higher breakdown voltage and decreased output conductance. A very high power density of 7.8 W/mm was measured on-wafer at 3 GHz for a two-finger 400-/spl mu/m gate periphery SiC MESFET. The PAE for this device was 70% at class AB bias. Two-tone measurements at 3 GHz /spl plusmn/ 100 kHz indicate an optimum FP length for high linearity operation.
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| 2. |
- Nilsson, Per-Åke, 1964, et al.
(author)
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Influence of Field Plates and Surface Traps on Microwave Silicon Carbide MESFETs
- 2008
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In: IEEE Transactions on Electron Devices. - 1557-9646 .- 0018-9383. ; 55:8, s. 1875-1879
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Journal article (peer-reviewed)abstract
- The influence of field plates and surface traps on silicon carbide MESFETs for microwave operation was investigated. By increasing the length of gate-connected field plates from 50 to 800 nm, it was possible to increase the gate–drain breakdown voltage of the devices from 125 to 170 V. At the same time, the current slump effect of traps in the passivation oxide was reduced. By using a combination of field plates and a passivation oxide with low interface trap density, it was possible to reach an output power density of 8 W/mm at 3 GHz.
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| 5. |
- Vidarsson, Arnar M., et al.
(author)
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Observations of very fast electron traps at SiC/high-κ dielectric interfaces
- 2023
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In: APL Materials. - : AIP Publishing. - 2166-532X. ; 11:11
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Journal article (peer-reviewed)abstract
- Very fast interface traps have recently been suggested to be the main cause behind poor channel-carrier mobility in SiC metal-oxide-semiconductor field effect transistors. It has been hypothesized that the NI traps are defects located inside the SiO2 dielectric with energy levels close to the SiC conduction band edge and the observed conductance spectroscopy signal is a result of electron tunneling to and from these defects. Using aluminum nitride and aluminum oxide as gate dielectrics instead of SiO2, we detect NI traps at these SiC/dielectric interfaces as well. A detailed investigation of the NI trap density and behavior as a function of temperature is presented and discussed. Advanced scanning transmission electron microscopy in combination with electron energy loss spectroscopy reveals no SiO2 at the interfaces. This strongly suggests that the NI traps are related to the surface region of the SiC rather than being a property of the gate dielectric.
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| 8. |
- Fagerlind, Martin, 1980, et al.
(author)
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Investigation of the interface between silicon nitride passivations and AlGaN/AlN/GaN heterostructures by C(V) characterization of metal-insulator-semiconductor-heterostructure capacitors
- 2010
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In: Journal of Applied Physics. - : AIP Publishing. - 0021-8979 .- 1089-7550. ; 108:1
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Journal article (peer-reviewed)abstract
- Capacitance-voltage [C(V)] measurements of metal-insulator-semiconductor-heterostructure capacitors are used to investigate the interface between silicon nitride passivation and AlGaN/AlN/GaN heterostructure material. AlGaN/AlN/GaN samples having different silicon nitride passivating layers, deposited using three different deposition techniques, are evaluated. Different interface state distributions result in large differences in the C(V) characteristics. A method to extract fixed charge as well as traps from the C(V) characteristics is presented. Rough estimates of the emission time constants of the traps can be extracted by careful analysis of the C(V) characteristics. The fixed charge is positive for all samples, with a density varying between 1.3 x 10(12) and 7.1 x 10(12) cm(-2). For the traps, the peak density of interface states is varying between 16 x 10(12) and 31 x 10(12) cm(-2) eV(-1) for the three samples. It is concluded that, of the deposition methods investigated in this report, the low pressure chemical vapor deposited silicon nitride passivation shows the most promising results with regards to low densities of interface states. (C) 2010 American Institute of Physics. [doi:10.1063/1.3428442]
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| 9. |
- Gudjonsson, Gudjon, 1973, et al.
(author)
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Design and Fabrication of 4H-SiC RF MOSFETs
- 2007
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In: IEEE Transactions on Electron Devices. - 1557-9646 .- 0018-9383. ; 54:12, s. 3138-3145
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Journal article (peer-reviewed)abstract
- We present simulations, fabrication and analysis of 4H-SiC RF power MOSFETs. We obtain an extrinsic transition frequency of 11.2 GHz and an f max = 11.9 GHz, a breakdown voltage above 200 V and an output power of 1.9 W/mm at 3 GHz. The measured devices are double fingered, source-gate-draingate-source with 2 × 0.4 mm total gate width and the nominal channel length of the devices is 0.5 μm. To the authors knowledge, this is the highest transition frequency and output power density ever reported for SiC RF MOSFETs. The antipunchthrough is introduced as a way to take advantage of the SiC's material properties. A detailed description of the device processing is also given. © 2007 IEEE.
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