| 1. |
- Lundgren, Jan, 1977-
(author)
-
Simulating Behavioral Level On-Chip Noise Coupling
- 2007
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Doctoral thesis (other academic/artistic)abstract
- In this thesis, noise coupling simulation is introduced into the behavioral level. Methods andmodels for simulating on-chip noise coupling at the behavioral level in a design flow are presentedand verified for accuracy and validity. Today, designs of electronic systems are becoming denserand more and more mixed-signal systems such as System-on-Chip (SoC) are being devised. Thisraises problems when the electronics components start to interfere with each other. Often, digitalcomponents disturb analog components, introducing noise into the system causing degradation ofthe performance or even introducing errors into the functionality of the system.Today, these effects can only be simulated at a very late stage in the design process, causinglarge design iterations and increased costs if the designers are required to return and makealterations, which may have occurred at a very early stage in the process.This is why the focus of this work is centered on extracting noise coupling simulation modelsthat can be used at a very early design stage, such as at the behavioral level and then follow thedesign through the various design stages. To achieve this, SystemC is selected as a platform andimplementation example for the behavioral level models. SystemC supports design refinement,which means that when designs are being refined and are crossing the design levels, the noisecoupling models can also be refined to suit the current design.This new method of thinking in primarily mixed-signal designs is called Behavioral levelNoise Coupling (BeNoC) simulation and shows great promise in enabling a reduction in the costsof design iterations due to component cross-talk and simplifies the work for mixed-signal systemdesigners.
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| 2. |
- Pasha, Muhammad Touqir, 1982-
(author)
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All-Digital PWM Transmitters
- 2019
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Doctoral thesis (other academic/artistic)abstract
- Electronic devices with wireless connectivity are fast becoming a part of daily life. According to some estimates, in the next five years, 10 billion new devices with internet connectivity would be produced. To lower the costs and extend the battery life of electronic circuits, there is an increased interest in using lowcost, low-power CMOS circuits. By taking advantage of the higher integration capabilities of modern CMOS, the analog, digital, and radio circuits can be integrated on a single die, typically called a radio-frequency system-on-chip (RF-SoC).In an RF-SoC, most of the power is usually consumed by the radio circuits, especially the power amplifier (PA). Hence, to take advantage of the improved switching capability of transistors in modern CMOS, the use of switch-mode PAs (SMPAs) is becoming more popular. SMPAs exhibit a much higher efficiency as compared to their linear counterparts and can be easily integrated with the digital baseband circuits.To satisfy the demand for higher data throughput, modern wireless standards like LTE and IEEE 802.11 generate envelope-varying signals using advanced modulation schemes like M-QAM and OFDM. Among several other techniques, pulse-width modulation (PWM) allows for the amplification of the envelopevarying signals using SMPAs.The first part of this thesis explores techniques to improve the spectral performance of PWM-based transmitters. The proposed transmitters are fully digital, and the entire signal chain up to the PA can be implemented using the digital design flow, which is especially beneficial in sub-micron CMOS processes with low voltage headroom. A new transmitter is proposed that compensates for the aliasing distortion in polar PWM transmitters by using outphasing. The transmitter exhibits an improvement of up to 9 dB in dynamic range for a 1.4 MHz LTE uplink signal. The idea is extended to compensate for both image and aliasing distortions in all-digital implementations of polar PWM transmitters. By using a field programmable gate array (FPGA) and Class-D SMPAs, the proposed transmitter shows an improvement of up to 6.9 dBc in the adjacent channel leakage ratio (ACLR) and 10% in the error vector magnitude (EVM) for a 20 MHz LTE uplink signal. The proposed transmitter is fully programmable and can be easily adapted for multi-band and multi-standard transmission.To enhance the phase linearity of all-digital PWM transmitters, a new transmitter architecture based on outphasing is presented. The proposed transmitter uses outphasing to improve the phase resolution and exhibits an improvement of 2.8 dBc and 3.3% in ACLR and EVM, respectively.The difference between the polar and quadrature implementations of RFPWM based transmitters is explored. By using mathematical derivations and simulations, it is shown that the polar implementation outperforms the quadrature implementation due to the lower quantization noise. An RF-PWM based transmitter that eliminates both image and aliasing distortions is presented. The proposed transmitter has an all-digital implementation, uses a single SMPA, and eliminates the need for a power combiner resulting in a more compact design. For a 1.4 MHz LTE uplink signal, the proposed transmitter exhibits an improvement of up to 11.3 dBc in ACLR.The second part of this work focuses on the design of all-digital area-efficient architectures of time-to-digital converters (TDCs). A TDC is essentially a stopwatch with a pico-second resolution and can be used to accurately quantify the pulse width and position of PWM signals.A Vernier delay line-based TDC is presented that replaces the conventionally used sampling D flip-flops by a single transistor. This resulting implementation does not suffer from blackout time associated with D flip-flops allowing for a more compact design. The proposed TDC achieves a time resolution of 5.7 ps, and consumes 1.85 mW of power while operating at 50 MS/s.A modified switching scheme to reduce the power consumed by the thermometerto- binary encoder used in the TDCs is presented. By taking advantage of the operating nature of the TDCs, the proposed switching scheme reduces the power consumption by up to 40% for a 256-bit encoder.
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| 3. |
- Touqir Pasha, Muhammad
(author)
-
Circuit Design for All-Digital Frequency Synthesizers
- 2014
-
Licentiate thesis (other academic/artistic)abstract
- The market for low cost portable electronics is rapidly growing. Physical activity monitors, portable music players, and smart watches are fast becoming a part of daily life. As the market for wearable devices has grown, a primary concern for IC manufacturers is to provide low cost, low power and lightweight circuit solutions. In a bid to lower the costs and extend battery life there is an increased interest in using low-cost, low-power CMOS processes. As a result fully integrated systems on chips (SOC) have been realized that efficiently perform the required functions. These SOCs house digital, analog and in some cases radio circuits on a single die in a bid to reduce cost and improve productivity.Phase Locked Loops (PLLs) are a key building block for all SOCs where they are used to generate clock signals for synchronous systems. In monolithic implementations the design cost of a circuit is measured in terms of the silicon area and not the number of devices in the circuit. With the advent of all-digital techniques, there is a renewed interest in the design of compact PLLs as the area occupied by the traditional PLLs is very large due to the presence of large passive components in the loop filter and the oscillator. As a result, various digital circuit design techniques are being explored to design compact all-digital PLLs (ADPLLs) while satisfying the performance requirements for the target applications.The focus of this work is to explore new techniques for area, power and time efficient design of ADPLL component blocks. The first part of this works focuses on the feasibility of using automatic place and route (P&R) tools to synthesize a time-to-digital converter (TDC). An area efficient TDC is synthesized in a 65 nm CMOS process using automated P&R which exhibits a time resolution of 6.5 ps with an input sampling rate of 100 MS/s while occupying an area of 0.002 mm2. A modified switching scheme is also presented which reduces the power consumption of the thermometer-to-binary encoder by up to 40%.The second part of this thesis proposes a power supply filter for mitigating the affect of cyclostationary noise on the voltage controlled ring oscillator. The key idea is to raise the impedance in the current supply during the sensitive periods and lower it during insensitive periods of the oscillator operation. To demonstrate the feasibility of the proposed filter, a pseudo differential ring oscillator is designed in a 65 nm CMOS process which exhibits an rms jitter of less than 14 ps at 2.4 GHz in the presence of a 500 mV noise tone in the power supply.
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| 4. |
- Andersson, Niklas, 1975-
(author)
-
Design of Integrated Building Blocks for the Digital/Analog Interface
- 2015
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Doctoral thesis (other academic/artistic)abstract
- The integrated circuit has, since it was invented in the late 1950's, undergone a tremendous development and is today found in virtually all electric equipment. The small feature size and low production cost have made it possible to implement electronics in everyday objects ranging from computers and mobile phones to smart prize tags. Integrated circuits are typically used for data communication, signal processing and data storage. Data is usually stored in digital format but signal processing can be performed both in the digital and in the analog domain. For best performance, the right partition of signal processing between the analog and digital domain must be used. This is made possible by data converters converting data between the domains. A device converting an analog signal into a digital representation is called an analog-to-digital converter (ADC) and a device converting digital data into an analog representation is called a digital-to-analog converter (DAC). In this work we present research results on these data converters and the results are compiled in three different categories. The first contribution is an error correction technique for DACs called dynamic element matching, the second contribution is a power efficient time-to-digital converter architecture and the third is a design methodology for frequency synthesis using digital oscillators.The accuracy of a data converter, i.e., how accurate data is converted, is often limited by manufacturing errors. One type of error is the so-called matching error and in this work we investigate an error correction technique for DACs called dynamic element matching (DEM). If distortion is limiting the performance of a DAC, the DEM technique increases the accuracy of the DAC by transforming the matching error from being signal dependent, which results in distortion, to become signal independent noise. This noise can then be spectrally shaped or filtered out and hereby increasing the overall resolution of the system. The DEM technique is investigated theoretically and the theory is supported by measurement results from an implemented 14-bit DAC using DEM. From the investigation it is concluded that DEM increases the performance of the DAC when matching errors are dominating but has less effect at conversion speeds when dynamic errors dominate.The next contribution is a new time-to-digital converter (TDC) architecture. A TDC is effectively an ADC converting a time difference into a digital representation. The proposed architecture allows for smaller and more power efficient data conversion than previously reported and the implemented TDC prototype is smaller and more power efficient as compared to previously published TDCs in the same performance segment.The third contribution is a design methodology for frequency synthesis using digital oscillators. Digital oscillators generate a sinusoidal output using recursive algorithms. We show that the performance of digital oscillators, in terms of amplitude and frequency stability, to a large extent depends on the start conditions of the oscillators. Further we show that by selecting the proper start condition an oscillator can be forced to repeat the same output sequence over and over again, hence we have a locked oscillator. If the oscillator is locked there is no drift in amplitude or frequency which are common problems for recursive oscillators not using this approach. To find the optimal start conditions a search algorithm has been developed which has been thoroughly tested in simulations. The digital oscillator output is used for test signal generation for a DAC or used to generate tones with high spectral purity using DACs.
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| 5. |
- Unnikrishnan, Vishnu
(author)
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Design of VCO-based ADCs
- 2016
-
Doctoral thesis (other academic/artistic)abstract
- Today's complex electronic systems with billions of transistors on a single die are enabled by the aggressive scaling down of the device feature size at an exponential rate as predicted by the Moore's law. Digital circuits benefit from technology scaling to become faster, more energy efficient as well as more area efficient as the feature size is scaled down. Moreover, digital design also benefits from mature CAD tools that simplify the design and cross-technology porting of complex systems, leveraging on a cell-based design methodology. On the other hand, the design of analog circuits is getting increasingly difficult as the feature size scales down into the deep nanometer regime due to a variety of reasons like shrinking voltage headroom, reducing intrinsic gain of the devices, increasing noise coupling between circuit nodes due to shorter distances etc. Furthermore, analog circuits are still largely designed with a full custom design ow that makes their design and porting tedious, slow, and expensive. In this context, it is attractive to consider realizing analog/mixed-signal circuits using standard digital components. This leads to scaling-friendly mixed-signal blocks that can be designed and ported using the existing CAD framework available for digital design. The concept is already being applied to mixed-signal components like frequency synthesizers where all-digital architectures are synthesized using standard cells as basic components. This can be extended to other mixed-signal blocks like digital-to-analog and analog to- digital converters as well, where the latter is of particular interest in this thesis.A voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) is an attractive architecture to achieve all-digital analog-to digital conversion due to favorable properties like shaping of the quantization error, inherent anti-alias filtering etc. Here a VCO operates as a signal integrator as well as a quantizer. A converter employing a ring oscillator as the VCO lends itself to an all-digital implementation.In this dissertation, we explore the design of VCO-based ADCs synthesized using digital standard cells with the long-term goal of achieving high performance data converters built from low accuracy switch components. In a first step, an ADC is designed using vendor supplied standard cells and fabricated in a 65 nm CMOS process. The converter delivers an 8-bit ENOB over a 25 MHz bandwidth while consuming 3.3 mW of power resulting in an energy efficiency of 235 fJ/step (Walden FoM). Then we utilize standard digital CAD tools to synthesize converter designs that are fully described using a hardware description language. A polynomial-based digital post-processing scheme is proposed to correct for the VCO nonlinearity. In addition, pulse modulation schemes like delta modulation and asynchronous sigma-delta modulation are used as a signal pre-coding scheme, in an attempt to reduce the impact of VCO nonlinearity on converter performance. In order to investigate the scaling benefits of all-digital data conversion, a VCO-based converter is designed in a 28 nm CMOS process. The design delivers a 13.4-bit ENOB over a 5 MHz bandwidth achieving an energy efficiency of 4.3 fJ/step according to post-synthesis schematic simulation, indicating that such converters have the potential of achieving good performance in deeply scaled processes by exploiting scaling benefits. Furthermore, large conversion errors caused by non-ideal sampling of the oscillator phase are studied. An encoding scheme employing ones counters is proposed to code the sampled ring oscillator output into a number, which is resilient to a class of sampling induced errors modeled by temporal reordering of the transitions in the ring. The proposed encoding reduces the largest error caused by random reordering of up to six subsequent bits in the sampled signal from 31 to 2 LSBs. Finally, the impact of process, voltage, and temperature (PVT) variations on the performance while operating the converter from a subthreshold supply is investigated. PVT-adaptive solutions are suggested as a means to achieve energy-efficient operation over a wide range of PVT conditions.
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| 6. |
- Afzal, Nadeem
(author)
-
Complexity and Power Reduction in Digital Delta-Sigma Modulators
- 2014
-
Doctoral thesis (other academic/artistic)abstract
- A number of state-of-the-art low power consuming digital delta-sigma modulator (ΔΣ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ΔΣ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ΔΣ topologies, error-feedback modulators (EFM) are well suited for so called digital to digital modulation.In order to meet the demands, various modifications to the conventional EFM architectures have been proposed. It is observed that if the internal and external digital signals of the EFM are not properly scaled then not only the design itself but also the signal processing blocks placed after it, may be over designed. In order to avoid the possible wastage of resources, a number of scaling criteria are derived. In this regard, the total number of signal levels of the EFM output is expressed in terms of the input scale, the order of modulation and the type of the loop filter.Further on, it is described that the architectural properties of a unit element-based DAC allow us to move some of the digital processing of the EFM to the analog domain with no additional hardware cost. In order to exploit the architectural properties, digital circuitry of an arbitrary-ordered EFM is split into two parts: one producing the modulated output and another producing the filtered quantization noise. The part producing the modulated output is removed after representing the EFM output with a set of encoded signals. For both the conventional and the proposed EFM architectures, the DAC structure remains unchanged. Thus, savings are obtained since the bits to be converted are not accumulated in the digital domain but instead fed directly to the DAC.A strategy to reduce the hardware of conventional EFMs has been devised recently that uses multiple cascaded EFM units. We applied the similar approach but used several cascaded modified EFM units. The compatibility issues among the units (since the output of each proposed EFM is represented by the set of encoded signals) are resolved by a number of architectural modifications. The digital processing is distributed among each unit by splitting the primary input bus. It is shown that instead of cascading the EFM units, it is enough to cascade their loop filters only. This leads not only to area reduction but also to the reduction of power consumption and critical path.All of the designs are subjected to rigorous analysis and are described mathematically. The estimates of area and power consumption are obtained after synthesizing the designs in a 65 nm standard cell library provided by the foundry.
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| 7. |
- Backenius, Erik, 1974-
(author)
-
Reduction of Substrate Noise in Mixed-Signal Circuits
- 2007
-
Doctoral thesis (other academic/artistic)abstract
- In many consumer products, e.g., cellular phones and handheld computers, both digital and analog circuits are required. Nowadays, it is possible to implement a large subsystem or even a complete system, that earlier required several chips, on a single chip. A system on chip (SoC) has generally the advantages of lower power consumption and a smaller fabrication cost compared with multi-chip solutions. The switching of digital circuits generates noise that is injected into the silicon substrate. This noise is known as substrate noise and is spread through the substrate to other circuits. The substrate noise received in an analog circuit degrades the performance of the circuit. This is a major design issue in mixed-signal ICs where analog and digital circuits share the same substrate.Two new noise reduction methods are proposed in this thesis work. The first focuses n reducing the switching noise generated in digital clock buffers. The strategy is to use a clock with long rise and fall times in conjunction with a special D flip-flop. It relaxes the constraints on the clock distribution net, which also reduce the design effort. Measurements on a test chip implemented in a 0.35 μm CMOS technology show that the method can be implemented in an IC with low cost in terms of speed and power consumption. A noise reduction up to 50% is obtained by using the method. The measured power consumption of the digital circuit, excluding the clock buffer, increased 14% when the rise and fall times of the clock were increased from 0.5 ns to 10 ns. The corresponding increase in propagation delay was less than 0.5 ns corresponding to an increase of 50% in propagation delay of the registers.The second noise reduction method focuses on reducing simultaneous switching noise below half the clock frequency. This frequency band is assumed to be the signal band of an analog circuit. The idea is to use circuits that have as close to periodic power supply currents as possible to obtain low simultaneous switching noise below the clock in the frequency domain. For this purpose we use precharged differential cascode switch logic together with a novel D flip-flop. To evaluate the method two pipelined adders have been implemented on transistor level in a 0.13 μm CMOS technology, where the novel circuit is implemented with our method and the reference circuit with static CMOS logic together with a TSPC D flip-flop. According to simulation results, the frequency components in the analog signal band can be attenuated from 10 dB up to 17 dB using the proposed method. The cost is mainly an increase in power consumption of almost a factor of three.Comparisons between substrate coupling in silicon-on-insulator (SOI) and conventional bulk technology are made using simple models. The objective is to get an understanding of how the substrate coupling differs in SOI from the bulk technology. The results show that the SOI has less substrate coupling if no guard band is used, up to a certain frequency that is dependent of the test case. Introducing a guard band resulted in a higher attenuation of substrate noise in bulk than in SOI.An on-chip measurement circuit aiming at measuring simultaneous switching noise has been designed in a 0.13 μm SOI CMOS technology. The measuring circuit uses a single comparator per channel where several passes are used to capture the waveform. Measurements on a fabricated testchip indicate that the measuring circuit works as intended.A small part of this thesis work has been done in the area of digit representation in digital circuits. A new approach to convert a number from two’s complement representation to a minimum signed-digit representation is proposed. Previous algorithms are working either from the LSB to the MSB (right-to-left) or from the MSB to the LSB (left-to-right). The novelty in the proposed algorithm is that the conversion is done from left-to-right and right-to-left concurrently. Using the proposed algorithm, the critical path in a conversion circuit can be nearly halved compared with the previous algorithms. The area and power consumption, of the implementation of the proposed algorithm, are somewhere between the left-to-right and right-to-left implementations.
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| 8. |
- Vesterbacka, Mark, 1966-
(author)
-
Om implementation of maximally fast wave digital filters
- 1997
-
Doctoral thesis (other academic/artistic)abstract
- An approach to design and implement fixed-function digital filters using bit-serial arithmetic is proposed. The resulting implementations are maximally fast, i.e., the maximal sample frequency fmax is equal to the upper bound on the sample frequency given by the recursive parts of the algorithm. Such implementations are of interest for use in applications with high throughput or in low-power applications after supply voltage scaling. The throughput of the resulting implementations is comparable to the corresponding bit-parallel implementations while using a fractional amount of hardware resources. The proposed implementation technique can easily be extended to more general recursive algorithms.A maximally fast implementation is achieved by mapping of the operations in an algorithm to a cyclic schedule involving several sample intervals followed by an isomorphic mapping of the operations to a hardware structure. The ability to find maximally fast implementations with the proposed scheduling method is based on a decoupling of the sample period from the scheduling period. Further, numerical equivalence transformations are applied to the signal-flow graph to find a new algorithm with a reduced iteration period.Different latency models for the arithmetic operations are proposed and their effect on fmax is discussed. One of the models combined with canonic signed-digit coding of the coefficients yields significantly increased throughput for serial/parallel multipliers. It is shown that the circuit style and the interconnection of processing elements also must be taken into account to determine the iteration period bound. In a number of implementations it is demonstrated that higher throughput is obtained for a recursive filter by increasing the latency of the adders.New algorithms for full-precision serial computation of squares and serial/serial computation of products that yield minimal latency are derived. The logic realizations of the algorithms are regular and can be partitioned into modular bit-slices suitable for hardware implementation.A CAD tool is proposed that implements the operation scheduling and performs the hardware mapping. The tool accepts coefficients describing the filter and produces a synthesizable VHDL hardware netlist. The tool is capable of handling three different latency models and two lattice wave digital filter structures.
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