| 1. |
- Carpenter, Sona, 1983, et al.
(author)
-
A G-Band (140-220 GHz) planar stubbed branch-line balun in BCB technology
- 2013
-
In: 2013 3rd Asia-Pacific Microwave Conference, APMC 2013, Seoul, South Korea, 5-8 November 2013. - 9781479914746 ; , s. 273-275
-
Conference paper (peer-reviewed)abstract
- A G-Band planar stubbed branch-line balun isdesigned and fabricated in 3μm thick BCB technology. Thistopology of the balun does not need thru-substrate via hole orthin-film resistor which makes it extremely suitable for realizationon single-layer high-resistivity substrates commonly used atmillimeter-wave or post-processed BCB layers on top of standardsemi-insulating wafers. The design is simulated and validated bymeasurements. Measurement results on two fabricated back-tobackbaluns show better than 10 dB input and output return lossand 3.2 dB insertion loss from 140 to 220 GHz.
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| 2. |
- Moschetti, Giuseppe, 1982, et al.
(author)
-
Cryogenic InAs/AlSb HEMT Wideband Low-Noise IF Amplifier for Ultra-Low-Power Applications
- 2012
-
In: IEEE Microwave and Wireless Components Letters. - 1558-1764 .- 1531-1309. ; 22:3, s. 144-146
-
Journal article (peer-reviewed)abstract
- A cryogenic wideband 4-8 GHz hybrid low-noise amplifier, based on a 110 nm gate length InAs/AlSb HEMT process is presented. At room temperature the three-stage amplifier exhibited a transducer gain of 29 dB and a noise temperature of 150 K with 17.6 mW power consumption. When cooled to 13 K, the amplifier showed a minimum noise temperature of 19 K at a power consumption of 6 mW (66% reduction compared to room temperature). At cryogenic temperature, the optimum drain voltage for best noise performance was reduced from 0.55 V down to 0.3 V, demonstrating the very low-power and low-voltage capabilities of InAs/AlSb HEMT based low-noise amplifiers at cryogenic temperature.
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| 3. |
- Moschetti, Giuseppe, 1982, et al.
(author)
-
Cryogenic Operation of InAs/AlSb HEMT Hybrid LNAs
- 2012
-
In: 15th European Microwave Week - Space for Microwaves Conference Proceedings. Amsterdam, NETHERLANDS. OCT 28-NOV 02, 2012. - 9782874870286 ; , s. 373-376
-
Conference paper (peer-reviewed)abstract
- The suitability of InAs/AlSb HEMTs for cryogenic ultra low-power applications is investigated. Compared to room temperature, the device exhibited significantly improved drain current saturation, higher peak transconductance and lower gate current leakage at around 10 K. When tested in a three-stage hybrid 4-8 GHz LNA under cryogenic conditions, the LNA noise figure was 0.27 dB at an extremely low power consumption of 0.6 mW per stage.
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| 4. |
- Moschetti, Giuseppe, 1982, et al.
(author)
-
True planar InAs/AlSb HEMTs with ion-implantation technique for low-power cryogenic applications
- 2013
-
In: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 79, s. 268-273
-
Journal article (peer-reviewed)abstract
- In this paper, we report the room-temperature and cryogenic properties of true planar 110 nm InAs/AlSb HEMTs fabricated with Ar-ion isolation technology. Device isolation is generally improved and is in particular increased by four orders of magnitude at 6 K compared to 300 K. This results in improved drain current saturation, lower gate leakage current and 23% higher peak transconductance. The RF performance is significantly improved as well, with 47% higher f(T) (162 GHz) and 72% higher f(max) (155 GHz) at the low drain voltage of 0.1 V, compared to room temperature. The overall performance of the fabricated devices shows the suitability of ion implantation for the device isolation at cryogenic temperature. Furthermore, the excellent stability against oxidation and truly planar structure of these devices demonstrate great potential for highly integrated cryogenic millimeter-wave circuits in InAs/AlSb technology with ultra-low power consumption.
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| 5. |
- Abbasi, Morteza, 1982, et al.
(author)
-
A 80-95 GHz direct quadrature modulator in SiGe technology
- 2014
-
In: SiRF 2014 - 2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems. - 9781479915231 ; , s. 56-58
-
Conference paper (peer-reviewed)abstract
- A direct carrier IQ modulator operating in the 80-95 GHz frequency range is presented. The circuit is designed and fabricated in 0.18μm SiGe technology with 170/250 GHz fT/fmax. The modulator is based on double-balanced gilbert mixer cells with on-chip quadrature LO phase shifter and consumes 23mW DC power. In single-sideband operation, the chip exhibits up to 3 dB conversion gain below 85 GHz and -1± 0.5 dB up to 95 GHz. The image rejection ratio and LO-RF isolation are as high as 25 dB and 43 dB respectively. The modulator can operate with 10 GHz of modulation bandwidth and delivers -7 dBm power in saturation. For demonstration, the circuit is tested and shown to be capable of transmitting 4Gbps BPSK signal with NRZ rectangular pulses. The active chip area is 480μm× 260μm. © 2014 IEEE.
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| 6. |
- Abbasi, Morteza, 1982, et al.
(author)
-
A Broadband 60-to-120 GHz single-chip MMIC multiplier chain
- 2009
-
In: IEEE MTT-S International Microwave Symposium Digest. - 0149-645X. ; , s. 441-444
-
Conference paper (peer-reviewed)abstract
- This paper presents a single-chip 60 GHz to 120 GHz frequency multiplier chain based on 0.1 ?m GaAs mHEMT. The MMIC can deliver 3 to 5 dBm of output power from 110 GHz to 130 GHz with 2 dBm input power and consumes only 65 mW of DC power. The signal at the fundamental frequency is suppressed more than 20 dB over the band of interest. The impedance matching networks are realized using coupled transmission lines.
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| 7. |
- Abbasi, Morteza, 1982, et al.
(author)
-
A broadband differential cascode power amplifier in 45 nm CMOS for high-speed 60 GHz system-on-chip
- 2010
-
In: 2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010; Anaheim, CA; 23 May 2010 through 25 May 2010. - 1529-2517. ; , s. 978-142446242-1-
-
Conference paper (peer-reviewed)abstract
- A compact two-stage differential cascode power amplifier is designed and fabricated in 45 nm standard LP CMOS. The cascode configuration, with the common gate device placed in a separate P-well, provides reliable operating condition for the devices. The amplifier shows 20 dB small-signal gain centered at 60 GHz with a flat frequency response and 1-dB bandwidth of 10 GHz. The broadband large-signal operation is also ensured by providing constant load resistance to both stages over the entire band and coupling them with a dual resonance matching network. The chip delivers 11.2 dBm output power at 1-dB compression and up to 14.5 dBm power in saturation. The power amplifier operates with 2 V supply and draws 90 mA total current which results in 14.4% maximum PAE. The output third order intercept point is measured to be 18 dBm for two-tone measurement at 60 GHz with 0.5 GHz, 1 GHz and 2 GHz frequency separations. © 2010 IEEE.
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| 8. |
- Abbasi, Morteza, 1982, et al.
(author)
-
A direct conversion quadrature transmitter with digital interface in 45 nm CMOS for high-speed 60 GHz communications
- 2011
-
In: Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium. Baltimore, 5-7 June 2011. - 1529-2517. - 9781424482931
-
Conference paper (peer-reviewed)abstract
- A compact 60 GHz direct conversion quadrature transmitter is designed and fabricated in 45 nm standard LP CMOS. The transmitter features an integrated power amplifier with continuous output level control and interfaces binary data signals with nominal peak-to-peak voltage swing of 300 mV. The highest measured modulation bandwidth is limited by the measurement setup to 4 GHz but is simulated to be as high as 10 GHz. In single sideband up-converting operation mode, the measured image suppression ratio is 22 dB with 36 dB of carrier suppression corresponding to approximately 8% EVM in the output signal constellation. The output RF frequency can be from 54 GHz to 66 GHz to accommodate several channels and the output power can be adjusted from -3 dBm to 10 dBm. The chip is operated from a 2 V supply and draws 180 mA current.
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| 9. |
- Abbasi, Morteza, 1982, et al.
(author)
-
An E-Band(71-76, 81-86 GHz) Balanced Frequency Tripler for High-Speed Communications
- 2009
-
In: APMC: 2009 ASIA PACIFIC MICROWAVE CONFERENCE. - 9781424428014 ; 1-5, s. 1184-1187
-
Conference paper (other academic/artistic)abstract
- An E-Band transistor-based balanced frequency tripler is implemented using a 0.15 mu m GaAs mHEMT process which can be integrated into a single-chip RF front-end. The balanced configuration with 90 degrees hybrids at the input and output improves the port impedance matching which is measured to be better than 15 dB at the input and 10 dB at the output over the frequencies of interest. The tripler has a conversion loss of 11.5 dB from 71 GHz to 76 GHz and 14 dB from 81 GHz to 86 GHz. The second and forth harmonics are suppressed by more than 30 dB and the fundamental frequency by 20 dB. The tripler can deliver -2 dBm output power.
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| 10. |
- Abbasi, Morteza, 1982, et al.
(author)
-
Direct carrier quadrature modulator and Demodulator MMICs for 60 GHz gigabit wireless communications
- 2011
-
In: Asia-Pacific Microwave Conference Proceedings (APMC 2011; Melbourne, VIC; 5 - 8 December 2011). - 9780858259744 ; , s. 1134-1137
-
Conference paper (other academic/artistic)abstract
- A 60 GHz direct carrier quadrature modulator is designed and fabricated in 0.15 μm mHEMT technology. The design is based on passive mixers and therefore reciprocal which makes it possible to be used both as modulator and demodulator. The modulator has an input bandwidth of 0-5 GHz on each of the I and Q ports and an RF bandwidth of 53-68 GHz. Carrier leakage to the output port is eliminated by addition of an inductive path from the LO port to the RF port. The modulator requires 5 dBm LO power and can output up to -6 dBm RF power in linear region and up to -4 dBm when driven into saturation. When operated as an SSB mixer, the conversion loss is measured to be 11 dB and image and LO signals are suppressed by as much as 30 dB compared to the desired signal. For demonstration, a pair of the presented modulator/demodulator is used to transmit 7Gbps BPSK signal over 1m and 10Gbps QPSK signal over 0.5m wireless link.
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| 11. |
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| 12. |
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| 13. |
- Abbasi, Morteza, 1982, et al.
(author)
-
Single-Chip 220-GHz Active Heterodyne Receiver and Transmitter MMICs With On-Chip Integrated Antenna
- 2011
-
In: IEEE Transactions on Microwave Theory and Techniques. - 0018-9480 .- 1557-9670. ; 59:2, s. 466-478
-
Journal article (peer-reviewed)abstract
- This paper presents the design and characterization of single-chip 220-GHz heterodyne receiver (RX) and transmitter (TX) monolithic microwave integrated circuits (MMICs) with integrated antennas fabricated in 0.1-mu m GaAs metamorphic high electron-mobility transistor technology. The MMIC receiver consists of a modified square-slot antenna, a three-stage low-noise amplifier, and a sub-harmonically pumped resistive mixer with on-chip local oscillator frequency multiplication chain. The transmitter chip is the dual of the receiver chip by inverting the direction of the RF amplifier. The chips are mounted on 5-mm silicon lenses in order to interface the antenna to the free space and are packaged into two separate modules. The double-sideband noise figure (NF) and conversion gain of the receiver module are measured with the Y-factor method. The total noise temperature of 1310 +/- 100K(corresponding to an NF of 7.4 dB), including the losses in the lens and antenna, is measured at 220 GHz with a respective conversion gain of 3.5 dB. The radiated continuous-wave power from the transmitter module is measured to be up to -6 dBm from 212 to 226 GHz. The transmitter and receiver are linked in a quasi-optical setup and the IF to IF response is measured to be flat up to 10 GHz. This is verified to be usable for transmission of a 12.5-Gb/s data stream between the transmit and receive modules over a 0.5-m wireless link. The modules operate with a 1.3-V supply and each consume 110-mW dc power. The presented 220-GHz integrated circuits and modules can be used in a variety of applications, including passive and active imaging, as well as high-speed data communications. To the best of our knowledge, these MMICs are the highest frequency single-chip low-noise heterodyne receiver and transmitter pair reported to date.
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| 14. |
- Abbasi, Morteza, 1982, et al.
(author)
-
Single-Chip Frequency Multiplier Chains for Millimeter-Wave Signal Generation
- 2009
-
In: IEEE Transactions on Microwave Theory and Techniques. - 0018-9480 .- 1557-9670. ; 57:12, s. 3134-3142
-
Journal article (peer-reviewed)abstract
- Two single-chip frequency multiplier chains targeting 118 and 183 GHz output frequencies are presented. The chips are fabricated in a 0.1 mu m GaAs metamorphic high electron-mobility transistor process. The D-band frequency doubler chain covers 110 to 130 GHz with peak output power of 5 dBm. The chip requires 2 dBm input power and consumes only 65 mW of dc power. The signal at the fundamental frequency is suppressed more than 25 dB compared to the desired output signal over the band of interest. The G-band frequency sextupler (x6) chain covers 155 to 195 GHz with 0 dBm peak output power and requires 6.5 dBm input power and 92.5 mW dc power. The input signal to the multiplier chain can be reduced to 4 dBm while the output power drops only by 0.5 dB. The unwanted harmonics are suppressed more than 30 dB compared to the desired signal. An additional 183 GHz power amplifier is presented to be used after the x6 frequency multiplier chain if higher output power is required. The amplifier delivers 5 dBm output power with a small-signal gain of 9 dB from 155 to 195 GHz. The impedance matching networks are realized using coupled transmission lines which is shown to be a scalable and straightforward structure to use in amplifier design. Microstrip transmission lines are used in all the designs.
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| 15. |
- Angelov, Iltcho, 1943, et al.
(author)
-
On the High Frequency De-Embedding& Modeling of FET Devices
- 2009
-
In: 73rd ARFTG Microwave Measurement Conference Spring 2009 - Practical Applications of Nonlinear Measurements; Boston, MA; United States; 12 June 2009 through 12 June 2009. - 9781424434428 ; , s. 28-31
-
Conference paper (peer-reviewed)abstract
- At millimetre wave frequencies, deembedding techniques start to fail due to larger uncertainty in measurements. In this paper, various pads-transistor transitions are being analysed and measured. The usage of measurement versus simulation based characterisation of the embedding layout is evaluated. Applying suggested measuring, modelling extraction procedure, results up to 220 GHz are demonstrated.
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| 16. |
- Carpenter, Sona, 1983, et al.
(author)
-
A 115-155 GHz quadrature up-converting MMIC mixer in InP DHBT technology
- 2013
-
In: 2013 8th European Microwave Integrated Circuits Conference, EuMIC 2013 - Held as Part of 16th European Microwave Week, EuMW 2013. ; , s. 113-116
-
Conference paper (peer-reviewed)abstract
- This paper presents a millimeter-wave (mmWave)direct quadrature modulator in 0.25μm InP DHBT technology.The modulator operates over the frequency range of 115 GHz to155 GHz and is based on double balanced Gilbert mixer cells.The design is tested with a CW input signal at 1 GHz and 0 dBmLO power and exhibits up to 6 dB conversion gain and morethan 22 dB image rejection ratio. The LO signal is suppressedby more than 27 dB. The chip consumes 78 mW DC power andcan provide up to 3 dBm RF power in saturation. The activechip area is 560μm× 440μm.
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| 17. |
- Carpenter, Sona, 1983, et al.
(author)
-
A D-Band 48-Gbit/s 64-QAM/QPSK Direct-Conversion I/Q Transceiver Chipset
- 2016
-
In: IEEE Transactions on Microwave Theory and Techniques. - 0018-9480 .- 1557-9670. ; 64:4, s. 1285-1296
-
Journal article (peer-reviewed)abstract
- This paper presents design and characterization of single-chip 110–170-GHz ( -band) direct conversion in-phase/quadrature-phase (I/Q) transmitter (TX) and receiver (RX) monolithic microwave integrated circuits (MMICs), realized in a 250-nm indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology. The chipset is suitable for low-power ultrahigh-speed wireless communication and can be used in both homodyne and heterodyne architectures. The TX consists of an I/Q modulator, a frequency tripler, and a broadband three-stage power amplifier. It has single sideband (SSB) conversion gain of 25 dB and saturated output power of 9 dBm. The RX includes an I/Q demodulator with -band amplifier and 3 multiplier chain at the LO port. The RX provides a conversion gain of 26 dB and has noise figure of 9 dB. A 48-Gbit/s direct quadrature phase-shift keying (QPSK) data transmission using a 144-GHz millimeter-wave carrier signal is demonstrated with a bit error rate (BER) of 2.3 and energy efficiency of 7.44 pJ/bit. An 18-Gbit/s 64-quadrature amplitude modulation (QAM) signal was transmitted in heterodyne mode with measured TX-to-RX error vector magnitude (EVM) of less than 6.8% and spectrum efficiency of 3.6 bit/s/Hz. The TX and RX have dc power consumption of 165 and 192 mW, respectively. The chip area of each TX and RX circuit is 1.3mm by 0.9mm
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| 18. |
- Carpenter, Sona, 1983, et al.
(author)
-
Fully Integrated D-Band Direct Carrier Quadrature (I/Q) Modulator and Demodulator Circuits in InP DHBT Technology
- 2015
-
In: IEEE Transactions on Microwave Theory and Techniques. - 0018-9480 .- 1557-9670. ; 63:5, s. 1666-1675
-
Journal article (peer-reviewed)abstract
- This paper presents design and characterization of D-band (110-170 GHz) monolithic microwave integrated quadrature up-and down-converting mixer circuits with on-chip RF and local oscillator (LO) baluns. The circuits are fabricated in 250-nm indium-phosphide double heterojunction bipolar transistor technology. The mixers require an external LO signal and can be used as direct carrier quadrature modulator and demodulator to implement higher order quadrature amplitude modulation formats. The up-converter has a single-sideband (SSB) conversion gain of 6 dB with image and LO suppression of 32 and 27 dBc, respectively. The chip can provide maximum output RF power of 2.5 dBm, a third-order output intercept point of 4 dBm, and consumes 78-mW dc power. The down-converter exhibits 14-dB SSB conversion gain with 25-dB image rejection ratio, and 11.5-dB SSB noise figure. The chip consumes 74-mW dc power and can deliver maximum output IF power of 4 dBm. Both chips have the same size with active area of 560 mu m x 440 mu m including the RF and LO baluns.
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| 19. |
- Chehrenegar, Pirooz, 1964, et al.
(author)
-
Highly linear 1-3 GHz GaN HEMT low-noise amplifier
- 2012
-
In: IEEE MTT-S International Microwave Symposium Digest. - 0149-645X. - 9781467310871
-
Conference paper (peer-reviewed)abstract
- A highly linear low-noise amplifier (LNA) based on a commercial Gallium Nitride (GaN) high electron mobility transistor (HEMT) technology is presented. The amplifier can be operated at three frequency bands of 1, 2 and 3 GHz. The maximum measured gain is 31 dB at 1GHz and the output referred third-order intercept point (OIP3) is constant for all three frequency bands and equal to 41±1 dBm at a power consumption of L.2 W. A minimum noise figure (NF) of 0.5 dB is measured for the amplifier at the same bias point demonstrating the simultaneous linearity and low noise performance. The presented performance together with the reasonably low power consumption is outstanding in comparison with recently published amplifiers in GaN technology and available commercial GaAs LNAs.
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| 20. |
- Ferndahl, Mattias, 1973, et al.
(author)
-
Highly integrated E-band direct conversion receiver
- 2012
-
In: 2012 IEEE Compound Semiconductor Integrated Circuit Symposium, CSICS 2012, La Jolla, CA, 14 - 17 October 2012. - 1550-8781. - 9781467309295
-
Conference paper (peer-reviewed)abstract
- This paper presents a highly integrated 70-98 GHz direct conversion receiver with 3 stage LNA, x6 frequency multiplier with buffer amplifier, and IQ-mixer suitable for Eband radio communication. The LNA, x6 and IQ-mixer are also presented separately. The LNA covers 65 to 95 GHz with 15 dB gain and minimum 5.5 dB noise figure, x6 covers 71 to 91 GHz with 0 to 8 dBm output power and the IQ-mixer an RF frequency from 70 to 95 GHz and IF frequency from DC to 12 GHz with only 8 dB conversion loss and better than 15 dB image reject. The complete receiver circuit shows an RF bandwidth of 70 to 98 GHz, LO bandwidth of 75 to 92 GHz and IF bandwidth from DC to more than 12 GHz. The conversion gain is 3 to 6 dB with a noise figure of 5 to 7 dB, the image rejection 15 dB to as high as 28 dB, and the input 1 dB compression point -12 dBm.
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| 21. |
- Gavell, Marcus, 1981, et al.
(author)
-
An Image Reject Mixer for High-Speed E-band (71-76, 81-86 GHz) Wireless Communication
- 2009
-
In: Compound Semiconductor Integrated Circuit Symposium, Oct. 2009, Greensboro, NC. - : IEEE. - 1550-8781. - 9781424451913 ; , s. 1-4
-
Conference paper (peer-reviewed)abstract
- In this paper, the design and characterization of a broadband image reject mixer for the next generation of point-to-point microwave links is presented. The manufacturing has been made in a commercially available 0.15 μm gate length GaAs mHEMT technology. The measured performance demonstrates a conversion loss of 9 dB and an image rejection ratio of 25 dB on average across the full E-band (71-76 and 81-86 GHz). Performance peaks at 77 GHz with conversion loss of 7 dB and image rejection of 40 dB. Furthermore, these results have been achieved with a LO power requirement of 4 dBm. To the best of the authors' knowledge this is the first reported image reject mixer suitable for the full E-band. ©2009 IEEE.
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| 22. |
- Kjellberg, Torgil, 1962, et al.
(author)
-
A Compact Cascode Power Amplifier in 45-nm CMOS for 60-GHz Wireless Systems
- 2009
-
In: 2009 ANNUAL IEEE COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT SYMPOSIUM - 2009 IEEE CSIC SYMPOSIUM, TECHNICAL DIGEST 2009. - 1550-8781. - 9781424452606 ; , s. 95-98
-
Conference paper (peer-reviewed)abstract
- This paper presents a power amplifier in 45nm CMOS technology operating in the 50 to 60-GHz frequency range. It uses a single-ended topology with two cascode stages. A gain of 19.6 dB is obtained at 54 GHz where the gain peaks, and 17 dB at 60 GHz. The measured output-referred 1-dB compression point is 8.7 dBm at 60 GHz and a supply voltage of 2.1 V, and the saturated output power is 13.5 dBm. The bias conditions are shown to be reliable through lifetime measurements. The active chip-area measures 160 mu m x 110 mu m.
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| 23. |
- Rahiminejad, Sofia, 1987, et al.
(author)
-
A four level silicon microstructure fabrication by DRIE
- 2016
-
In: Journal of Microelectromechanical Systems. - : IOP Publishing. - 1057-7157. ; 26:8
-
Journal article (peer-reviewed)abstract
- We present a four level Si microstructure fabrication process with depths ranging from 70-400 μm. All four levels are etched from the same side, by using four hard masks (SiO2, Al, AZ4562 photo resist, and Al). The choice of the hard masks and their relative selectivity will be discussed. Also two different deep reactive ion etching (DRIE) processes, performed in two different machines, are compared and evaluated. The process evaluation and discussions are based on the vertical walls deviation from a right angle, the surface roughness and the resolution. In the end, a solution is proposed to remove spikes and grassing which appeared during both DRIE processes, and the impact of removing them from the surfaces is discussed.
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| 24. |
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| 25. |
- Svedin, Jan, et al.
(author)
-
An experimental 210 GHz radar system for 3D stand-off detection
- 2010
-
In: 35th International Conference on Infrared Millimeter and Terahertz Waves (IRMMW-THz), 2010. - 9781424466559
-
Conference paper (peer-reviewed)abstract
- A 210 GHz radar system for studies of personscanning at stand-off distances is presented. The radar uses amechanically scanned RX front-end based on an antennaintegratedMMIC. The TX part is based on an HBV quintupler.Image data formation is made using the FMCW and SARprinciples.
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