| 1. |
- Andersson, Helene, et al.
(författare)
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Hydrophobic valves of plasma deposited octafluorocyclobutane in DRIE channels
- 2001
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Ingår i: Sensors and actuators. B, Chemical. - 0925-4005 .- 1873-3077. ; 75:1-2, s. 136-141
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Tidskriftsartikel (refereegranskat)abstract
- The suitability of using octafluorocyclobutane (C4F8) patches as hydrophobic valves in microfluidic biochemical applications has been shown. A technique has been developed to generate lithographically defined C4F8 hydrophobic patches in deep reactive ion-etched silicon channels. Some of the advantages of this process are that no specific cleaning of the substrate is required, C4F8 is deposited on the sidewalls and the bottom of the channels, a standard photoresist mask can be used to define the patches, and that it is a fast and convenient dry chemical process performed by a standard inductively coupled plasma etcher using the Bosch process. Different patch lengths (200-1000 mum) of C4F8 were deposited in 50 mum wide channels to evaluate which size is most suitable for microfluidic biochemical applications. The valve function of the hydrophobic patches was tested for the following liquids: DD water, acetone, propanol, bead solution and a mixture used for pyrosequencing of DNA. Patch lengths of 200 mum of C4F8 successfully stopped each solution for at least 20 consecutive times. The C4F8 film resists water for at least 5 h. The hydrophobic valve also resists very high concentrations (25%) of surfactants (Tween 80). C4F8 shows a much higher resistance towards water and surface active solutions than previous hydrophobic patches. However, 50% Tween 80 was not stopped at all by the hydrophobic patch. An applied pressure of 760 Pa at the inlet was needed for water to over-run the hydrophobic patch.
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| 2. |
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| 3. |
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| 4. |
- Antelius, Mikael, et al.
(författare)
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Hermetic integration of liquids in MEMS by room temperature, high-speed plugging of liquid-filled cavities at wafer level
- 2011
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Ingår i: Proceedings IEEE International Conference on Micro Electro Mechanical Systems (MEMS). - : IEEE. ; , s. 356-359
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- This paper reports a novel room temperature hermetic liquid sealing process based on wire bonded "plugs" over the access ports of liquid-filled cavities. The method enables liquids to be integrated already at the fabrication stage. Test vehicles were manufactured and used to investigate the mechanical and hermetic properties of the seals. A helium leak rate of better than 1E-10 mbarL/s was measured on the successfully sealed structures. The bond strength of the "plugs" were similar to standard wire bonds on flat surfaces.
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| 5. |
- Antelius, Mikael, et al.
(författare)
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Hermetic integration of liquids using high-speed stud bump bonding for cavity sealing at the wafer level
- 2012
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Ingår i: Journal of Micromechanics and Microengineering. - : IOP Publishing. - 0960-1317 .- 1361-6439. ; 22:4, s. 045021-
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Tidskriftsartikel (refereegranskat)abstract
- This paper reports a novel room-temperature hermetic liquid sealing process where the access ports of liquid-filled cavities are sealed with wire-bonded stud bumps. This process enables liquids to be integrated at the fabrication stage. Evaluation cavities were manufactured and used to investigate the mechanical and hermetic properties of the seals. Measurements on the successfully sealed structures show a helium leak rate of better than 10 (10) mbarL s (1), in addition to a zero liquid loss over two months during storage near boiling temperature. The bond strength of the plugs was similar to standard wire bonds on flat surfaces.
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| 6. |
- Antelius, Mikael, et al.
(författare)
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Room-temperature wafer-level vacuum sealing by compression of high-speed wire bonded gold bumps
- 2011
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Ingår i: Proceedings IEEE International Conference on Solid-State Sensors, Actuators, and Microsystems (Transducers). - : IEEE. ; , s. 1360-1363
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- This paper reports experimental results of a novel room temperature vacuum sealing process based on compressing wire bonded gold “bumps”, causing a material flow into the access ports of vacuum-cavities. The leak rate out of manufactured cavities was measured over 5 days and evaluated to less than the detection limit, 6×10-12 mbarL/s, per sealed port. The cavities have been sealed at a vacuum level below 10 mbar. The method enables sealing of vacuum cavities at room temperature using standard commercial tools and processes.
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| 7. |
- Antelius, Mikael, et al.
(författare)
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Small footprint wafer-level vacuum packaging using compressible gold sealing rings
- 2011
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Ingår i: Journal of Micromechanics and Microengineering. - : IOP Publishing. - 0960-1317 .- 1361-6439. ; 21:8, s. 085011-
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Tidskriftsartikel (refereegranskat)abstract
- A novel low-temperature wafer-level vacuum packaging process is presented. The process uses plastically deformed gold rings as sealing structures in combination with flux-free soldering to provide the bond force for a sealing wafer. This process enables the separation of the sealing and the bonding functions both spatially on the wafer and temporally in different process steps, which results in reduced areas for the sealing rings and prevents outgassing from the solder process in the cavity. This enables space savings and yields improvements. We show the experimental result of the hermetic sealing. The leak rate into the packages is determined, by measuring the package lid deformation over 10 months, to be lower than 3.5 x 10(-13) mbar l s(-1), which is suitable for most MEMS packages. The pressure inside the produced packages is measured to be lower than 10 mbar.
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| 8. |
- Antelius, Mikael, et al.
(författare)
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Wafer-Level Vacuum Sealing by Coining of Wire Bonded Gold Bumps
- 2013
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Ingår i: Journal of microelectromechanical systems. - 1057-7157 .- 1941-0158. ; 22:6, s. 1347-1353
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Tidskriftsartikel (refereegranskat)abstract
- This paper reports on the investigation of a novel room-temperature vacuum sealing method based on compressing wire bonded gold bumps which are placed to partially overlap the access ports into the cavity. The bump compression, which is done under vacuum, causes a material flow into the access ports, thereby hermetically sealing a vacuum inside the cavities. The sealed cavity pressure was measured by residual gas analysis to 8x10(-4) mbar two weeks after sealing. The residual gas content was found to be mainly argon, which indicates the source as outgassing inside the cavity and no measurable external leak. The seals are found to be mechanically robust and easily implemented by the use of standard commercial tools and processes.
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| 9. |
- Aparicio, Francisco J., et al.
(författare)
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Dye-based photonic sensing systems
- 2016
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Ingår i: Sensors and actuators. B, Chemical. - : Elsevier. - 0925-4005 .- 1873-3077. ; 228, s. 649-657
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Tidskriftsartikel (refereegranskat)abstract
- We report on dye-based photonic sensing systems which are fabricated and packaged at wafer scale. For the first time luminescent organic nanocomposite thin-films deposited by plasma technology are integrated in photonic sensing systems as active sensing elements. The realized dye-based photonic sensors include an environmental NO2 sensor and a sunlight ultraviolet light (UV) A+B sensor. The luminescent signal from the nanocomposite thin-films responds to changes in the environment and is selectively filtered by a photonic structure consisting of a Fabry-Perot cavity. The sensors are fabricated and packaged at wafer-scale, which makes the technology viable for volume manufacturing. Prototype photonic sensor systems have been tested in real-world scenarios. (C) 2016 Elsevier B.V. All rights reserved.
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| 10. |
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| 11. |
- Asiatici, Mikhail, et al.
(författare)
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Capacitive inertial sensing at high temperatures of up to 400 degrees C
- 2016
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Ingår i: Sensors and Actuators A-Physical. - : Elsevier. - 0924-4247 .- 1873-3069. ; 238, s. 361-368
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Tidskriftsartikel (refereegranskat)abstract
- High-temperature-resistant inertial sensors are increasingly requested in a variety of fields such as aerospace, automotive and energy. Capacitive detection is especially suitable for sensing at high temperatures due to its low intrinsic temperature dependence. In this paper, we present high-temperature measurements utilizing a capacitive accelerometer, thereby proving the feasibility of capacitive detection at temperatures of up to 400 degrees C. We describe the observed characteristics as the temperature is increased and propose an explanation of the physical mechanisms causing the temperature dependence of the sensor, which mainly involve the temperature dependence of the Young's modulus and of the viscosity and the pressure of the gas inside the sensor cavity. Therefore a static electromechanical model and a dynamic model that takes into account squeeze film damping were developed.
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| 12. |
- Asiatici, Mikhail, et al.
(författare)
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Through Silicon Vias With Invar Metal Conductor for High-Temperature Applications
- 2017
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Ingår i: Journal of microelectromechanical systems. - : IEEE Press. - 1057-7157 .- 1941-0158. ; 26:1, s. 158-168
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Tidskriftsartikel (refereegranskat)abstract
- Through silicon vias (TSVs) are key enablers of 3-D integration technologies which, by vertically stacking andinterconnecting multiple chips, achieve higher performances,lower power, and a smaller footprint. Copper is the mostcommonly used conductor to fill TSVs; however, copper hasa high thermal expansion mismatch in relation to the siliconsubstrate. This mismatch results in a large accumulation ofthermomechanical stress when TSVs are exposed to high temperaturesand/or temperature cycles, potentially resulting in devicefailure. In this paper, we demonstrate 300 μm long, 7:1 aspectratio TSVs with Invar as a conductive material. The entireTSV structure can withstand at least 100 thermal cycles from −50 °C to 190 °C and at least 1 h at 365 °C, limited bythe experimental setup. This is possible thanks to matchingcoefficients of thermal expansion of the Invar via conductor andof silicon substrate. This results in thermomechanical stressesthat are one order of magnitude smaller compared to copperTSV structures with identical geometries, according to finiteelement modeling. Our TSV structures are thus a promisingapproach enabling 2.5-D and 3-D integration platforms for hightemperatureand harsh-environment applications.
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| 13. |
- Ayala, Christopher L., et al.
(författare)
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Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts
- 2015
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 113, s. 157-166
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Tidskriftsartikel (refereegranskat)abstract
- Nanoelectromechanical (NEM) switches have the potential to complement or replace traditional CMOS transistors in the area of ultra-low-power digital electronics. This paper reports the demonstration of prototype circuits including the first 3-stage ring oscillator built using cell-level digital logic elements based on curved NEM switches. The ring oscillator core occupies an area of 30 mu m x 10 mu m using 6 NEM switches. Each NEM switch device has a footprint of 5 mu m x 3 mu m, an air gap of 60 mu m and is coated with amorphous carbon (a-C) for reliable operation. The ring oscillator operates at a frequency of 6.7 MHz, and confirms the simulated inverter propagation delay of 25 ns. The successful fabrication and measurement of this demonstrator are key milestones on the way towards an optimized, scaled technology with sub-nanosecond switching times, lower operating voltages and VLSI implementation.
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| 14. |
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| 15. |
- Bleiker, Simon J., et al.
(författare)
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Adhesive wafer bonding with ultra-thin intermediate polymer layers
- 2017
-
Ingår i: Sensors and Actuators A-Physical. - : Elsevier. - 0924-4247 .- 1873-3069. ; 260, s. 16-23
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Tidskriftsartikel (refereegranskat)abstract
- Wafer bonding methods with ultra-thin intermediate bonding layers are critically important in heterogeneous 3D integration technologies for many NEMS and photonic device applications. A promising wafer bonding approach for 3D integration is adhesive bonding. So far however, adhesive bonding processes relied on relatively thick intermediate adhesive layers. In this paper, we present an adhesive wafer bonding process using an ultra-thin intermediate adhesive layer with sub-200 nm thickness. We demonstrate adhesive bonding of silicon wafers with a near perfect bonding yield of >99% and achieve less than ±10% non-uniformity of the intermediate layer thickness across an entire 100 mm-diameter wafer. A bond strength of 4.8 MPa was measured for our polymer adhesive, which is considerably higher than previously reported for other ultra-thin film adhesives. Additionally, the adhesive polymer used in the proposed method features excellent chemical and mechanical stability. We also report on a potential strategy for mitigating the formation of micro-voids in the polymer adhesive at the bond interface. Furthermore, the polymer adhesive can be sacrificially removed by oxygen plasma etching for both isotropic and anisotropic release etching. The characteristics of the adhesive wafer bonding process and its compatibility with CMOS wafers, makes it very attractive for heterogeneous 3D integration processes targeted at CMOS-integrated NEMS and photonic devices.
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| 16. |
- Bleiker, Simon J., et al.
(författare)
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Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding
- 2016
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Ingår i: Micromachines. - Basel, Switzerland : Multidisciplinary Digital Publishing Institute (MDPI). - 2072-666X. ; 7:10, s. 192-
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Tidskriftsartikel (refereegranskat)abstract
- Device encapsulation and packaging often constitutes a substantial part of the fabrication cost of micro electro-mechanical systems (MEMS) transducers and imaging sensor devices. In this paper, we propose a simple and cost-effective wafer-level capping method that utilizes a limited number of highly standardized process steps as well as low-cost materials. The proposed capping process is based on low-temperature adhesive wafer bonding, which ensures full complementary metal-oxide-semiconductor (CMOS) compatibility. All necessary fabrication steps for the wafer bonding, such as cavity formation and deposition of the adhesive, are performed on the capping substrate. The polymer adhesive is deposited by spray-coating on the capping wafer containing the cavities. Thus, no lithographic patterning of the polymer adhesive is needed, and material waste is minimized. Furthermore, this process does not require any additional fabrication steps on the device wafer, which lowers the process complexity and fabrication costs. We demonstrate the proposed capping method by packaging two different MEMS devices. The two MEMS devices include a vibration sensor and an acceleration switch, which employ two different electrical interconnection schemes. The experimental results show wafer-level capping with excellent bond quality due to the re-flow behavior of the polymer adhesive. No impediment to the functionality of the MEMS devices was observed, which indicates that the encapsulation does not introduce significant tensile nor compressive stresses. Thus, we present a highly versatile, robust, and cost-efficient capping method for components such as MEMS and imaging sensors.
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| 17. |
- Bleiker, Simon J., et al.
(författare)
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Device with a waveguide supported on a substrate and method for its fabrication
- 2020
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Patent (populärvet., debatt m.m.)abstract
- ABSTRACT A device (1) and a method for fabricating such a device is described. The device (1) comprises a device layer (4), a substrate (2) defining a substrate plane (3). A device layer plane (5) is defined on the side of the device layer (4) facing the substrate (2). The device also comprises a waveguide (7) for guiding an electromagnetic wave. The waveguide (7) is supported on the substrate (2) via a support structure (6) extending from the substrate (2) to the device layer (4). The ratio of the largest distance (D1), perpendicular to the substrate plane (3), between a free surface of the waveguide (7) facing the substrate and any solid material to the height (h) of the waveguide (7) is more than 6, i.e. D1/h \textgreater 6. The ratio of the distance (D2), perpendicular to the substrate plane (3), between the device layer plane (5) and the substrate plane (3) to the height (h) of the waveguide (7) is more than 6, i.e. D2/h \textgreater 6.
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| 18. |
- Bleiker, Simon J.
(författare)
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Heterogeneous 3D Integration and Packaging Technologies for Nano-Electromechanical Systems
- 2017
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Three-dimensional (3D) integration of micro- and nano-electromechanical systems (MEMS/NEMS) with integrated circuits (ICs) is an emerging technology that offers great advantages over conventional state-of-the-art microelectronics. MEMS and NEMS are most commonly employed as sensor and actuator components that enable a vast array of functionalities typically not attainable by conventional ICs. 3D integration of NEMS and ICs also contributes to more compact device footprints, improves device performance, and lowers the power consumption. Therefore, 3D integration of NEMS and ICs has been proposed as a promising solution to the end of Moore’s law, i.e. the slowing advancement of complementary metal-oxide-semiconductor (CMOS) technology.In this Ph.D. thesis, I propose a comprehensive fabrication methodology for heterogeneous 3D integration of NEM devices directly on top of CMOS circuits. In heterogeneous integration, the NEMS and CMOS components are fully or partially fabricated on separate substrates and subsequently merged into one. This enables process flexibility for the NEMS components while maintaining full compatibility with standard CMOS fabrication. The first part of this thesis presents an adhesive wafer bonding method using ultra-thin intermediate bonding layers which is utilized for merging the NEMS components with the CMOS substrate. In the second part, a novel NEM switch concept is introduced and the performance of CMOS-integrated NEM switch circuits for logic and computation applications is discussed. The third part examines two different packaging approaches for integrated MEMS and NEMS devices with either hermetic vacuum cavities or low-cost glass lids for optical applications. Finally, a novel fabrication approach for through silicon vias (TSVs) by magnetic assembly is presented, which is used to establish an electrical connection from the packaged devices to the outside world.
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| 19. |
- Bleiker, Simon J., et al.
(författare)
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High-Aspect-Ratio Through Silicon Vias for High-Frequency Application Fabricated by Magnetic Assembly of Gold-Coated Nickel Wires
- 2015
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Ingår i: IEEE Transactions on Components, Packaging, and Manufacturing Technology. - : IEEE Press. - 2156-3950 .- 2156-3985. ; 5:1, s. 21-27
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, we demonstrate a novel manufacturing technology for high-aspect-ratio vertical interconnects for high-frequency applications. This novel approach is based on magnetic self-assembly of prefabricated nickel wires that are subsequently insulated with a thermosetting polymer. The high-frequency performance of the through silicon vias (TSVs) is enhanced by depositing a gold layer on the outer surface of the nickel wires and by reducing capacitive parasitics through a low-k polymer liner. As compared with conventional TSV designs, this novel concept offers a more compact design and a simpler, potentially more cost-effective manufacturing process. Moreover, this fabrication concept is very versatile and adaptable to many different applications, such as interposer, micro electromechanical systems, or millimeter wave applications. For evaluation purposes, coplanar waveguides with incorporated TSV interconnections were fabricated and characterized. The experimental results reveal a high bandwidth from dc to 86 GHz and an insertion loss of <0.53 dB per single TSV interconnection for frequencies up to 75 GHz.
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| 20. |
- Bleiker, Simon J., et al.
(författare)
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High-speed Metal-filling of Through-Silicon Vias (TSVs) by Parallelized Magnetic Assembly of Micro-Wires
- 2016
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Ingår i: 2016 IEEE 29th International Conference on Micro Electro Mechanical Systems (MEMS). - : Institute of Electrical and Electronics Engineers (IEEE). - 9781509019731 ; , s. 577-580
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Konferensbidrag (refereegranskat)abstract
- This work reports a parallelized magnetic assembly method for scalable and cost-effective through-silicon via (TSV) fabrication. Our fabrication approach achieves high throughput by utilizing multiple magnets below the substrate to assemble TSV structures on many dies in parallel. Experimental results show simultaneous filling of four arrays of TSVs on a single substrate, with 100 via-holes each, in less than 20 seconds. We demonstrate that increasing the degree of parallelization by employing more assembly magnets below the substrate has no negative effect on the TSV filling speed or yield, thus enabling scaled-up TSV fabrication on full wafer-level. This method shows potential for industrial application with an estimated throughput of more than 70 wafers per hour in one single fabrication module. Such a TSV fabrication process could offer shorter processing times as well as higher obtainable aspect ratios compared to conventional TSV filling methods.
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| 21. |
- Bogaerts, Wim, et al.
(författare)
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MORPHIC : Programmable Photonic Circuits enabled by Silicon Photonic MEMS
- 2020
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Ingår i: Proceedings Volume 11285 SPIE OPTO - 1-6 February 2020 Silicon Photonics XV. - : SPIE-Intl Soc Optical Eng.
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- In the European project MORPHIC we develop a platform for programmable silicon photonic circuits enabled by waveguide-integrated micro-electro-mechanical systems (MEMS). MEMS can add compact, and low-power phase shifters and couplers to an established silicon photonics platform with high-speed modulators and detectors. This MEMS technology is used for a new class of programmable photonic circuits, that can be reconfigured using electronics and software, consisting of large interconnected meshes of phase shifters and couplers. MORPHIC is also developing the packaging and driver electronics interfacing schemes for such large circuits, creating a supply chain for rapid prototyping new photonic chip concepts. These will be demonstrated in different applications, such as switching, beamforming and microwave photonics.
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| 22. |
- Bogaerts, Wim, et al.
(författare)
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Programmable Photonic Circuits powered by Silicon Photonic MEMS Technology
- 2022
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Ingår i: Photonic Networks and Devices, Networks 2022. - : Optica Publishing Group (formerly OSA).
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Konferensbidrag (refereegranskat)abstract
- Programmable photonic chips allow flexible reconfiguration of on-chip optical connections, controlled through electronics and software. We will present the recent progress of such complex photonic circuits powered by silicon photonic MEMS actuators.
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| 23. |
- Bogaerts, W., et al.
(författare)
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Programmable photonic circuits using silicon photonic MEMS
- 2021
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Ingår i: Optics InfoBase Conference Papers. - : The Optical Society.
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Konferensbidrag (refereegranskat)abstract
- We present a silicon photonics technology extended with low-power MEMS scalable to large circuits. This enables us to make photonic waveguide meshes that can be reconfigured using electronics and software.
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| 24. |
- Bogaerts, Wim, et al.
(författare)
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Programmable silicon photonic circuits powered by MEMS
- 2022
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Ingår i: Proceedings of SPIE - The International Society for Optical Engineering. - : SPIE-Intl Soc Optical Eng.
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Konferensbidrag (refereegranskat)abstract
- We present our work to extend silicon photonics with MEMS actuators to enable low-power, large scale programmable photonic circuits. For this, we start from the existing iSiPP50G silicon photonics platform of IMEC, where we add free-standing movable waveguides using a few post-processing steps. This allows us to implement phase shifters and tunable couplers using electrostatically actuated MEMS, while at the same time maintaining all the original functionality of the silicon photonics platform. The MEMS devices are protected using a wafer-level sealing approach and interfaced with custom multi-channel driver and readout electronics.
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| 25. |
- Bogaerts, Wim, et al.
(författare)
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Scaling programmable silicon photonics circuits
- 2023
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Ingår i: Silicon Photonics XVIII. - : SPIE-Intl Soc Optical Eng.
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Konferensbidrag (refereegranskat)abstract
- We give an overview the progress of our work in silicon photonic programmable circuits, covering the techn stack from the photonic chip over the driver electronics, packaging technologies all the way to the sof layers. On the photonic side, we show our recent results in large-scale silicon photonic circuits with diff tuning technologies, including heaters, MEMS and liquid crystals, and their respective electronic driving sch We look into the scaling potential of these different technologies as the number of tunable elements in a ci increases. Finally, we elaborate on the software routines for routing and filter synthesis to enable the pho programmer.
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