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1.	Carlberg, Patrick, et al. (author) Lift-off process for nanoimprint lithography 2003 In: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 67-8, s. 203-207 Conference paper (peer-reviewed)abstract We report a novel a lift-off method for nanoimprint lithography. This is a bi-layer method, using a polymethyl methacrylate (PMMA) on lift-off layer (LOL) resist scheme. For the imprint step, direct evidence for good pattern transfer down to 20 nm is shown. Oxygen plasma ashing is required to remove residual PMMA. A liquid solvent, MF 319, is used to transfer the pattern down to the silicon. The LOL is dissolved isotropically while the PMMA is unaffected. Ashing time can kept to a minimum through the wet etch method. This reduces the line widening effect. After metal evaporation a two-step lift-off process prevents metal flakes from adhering to the surface electrostatically. At first warm acetone breakes apart the metal layer and dissolves the PMMA, then warm Remover S-1165 removes the LOL and remaining metal. Structures of lines down to 50 nm and dots with a diameter of sub 20 nm are presented.
2.	Finder, C, et al. (author) Fluorescence microscopy for quality control in nanoimprint lithography 2003 In: Microelectronic Engineering (Proceedings of the 28th International Conference on Micro- and Nano-Engineering). - 0167-9317 .- 1873-5568. ; 67-8, s. 623-628 Conference paper (peer-reviewed)abstract Fluorescence microscopy is introduced as a low cost quality control process for nanoimprint lithography. To depict imprinted structures down to 1 mum lateral size and to detect residues down to 100 nm lateral size, the standard printable polymer mr-18000 is labelled with less than 0.1 wt.% fluorescent dye. Three different types of stamps are used to determine the dependence of the shape and size of stamp features in a series of imprints. The quality of a stamp is given by the sticking polymer residues per unit area. Fluorescence light images as well as visible light images are analysed. Changes in the area of the stamp covered with polymer as a function of the number of imprints is summarised in a statistical process chart. Adhesion was artificially induced in order to observe self cleaning of virgin stamps. They were detected and monitored, suggesting that this method is a suitable technique for quality control and that it could be easily adapted to the nanoimprint process. (C) 2003 Elsevier Science B.V. All rights reserved.
3.	Maximov, Ivan, et al. (author) Fabrication of Si-based nanoimprint stamps with sub-20 nm features 2002 In: MICROELECTRONIC ENGINEERING. - 1873-5568 .- 0167-9317. ; 61-2, s. 449-454 Conference paper (peer-reviewed)abstract We present two alternative methods for fabrication of nanoimprint lithography stamps in SiO2 with sub-20 nm features: (a) optimized electron beam lithography (EBL) and lift-off patterning of a 15-nm thick Cr mask, and (b) aerosol deposition of W particles in the 20-nm size range. In both cases, the pattern transfer into SiO2 was performed using reactive ion etching (RIE) with CHF3 as etch gas. In the first approach, we used a double layer resist system (PMMA/ZEP 520A7 positive resists) for the EBL exposure. Resist thickness, exposure dose and development time were optimized to obtain 15-20 nm features after Cr lift-off. In the second approach, we used size selected W aerosol particles as etch masks during etching of SiO2. Both methods of stamp fabrication are compared and discussed. (C) 2002 Published by Elsevier Science B.V.
4.	Zankovych, S, et al. (author) Nanoimprint-induced effects on electrical and optical properties of quantum well structures 2003 In: Microelectronic Engineering (Proceedings of the 28th International Conference on Micro- and Nano-Engineering). - 0167-9317 .- 1873-5568. ; 67-8, s. 214-220 Conference paper (peer-reviewed)abstract A study of optical and transport properties of semiconductor quantum well structures subjected to nanoimprint lithography (NIL), with its pressure and temperature cycles, has been undertaken to ascertain if this lithography technique induces detrimental changes in these properties of the active layers over a range of pressures and temperatures, typically used in this printing process. Ga0.47In0.53As-InP and GaAs-Al0.3Ga0.7As multiple quantum well samples were investigated. Luminescence and the photoluminescence excitation were recorded before and after printing. No impact upon the luminescence energy and intensity were detected. From the photoluminescence spectrum no evidence of induced strain was found. The magneto transport experiments yielded no evidence of deterioration of neither the mobility nor carrier concentration of a two-dimensional electron gas in a modulation-doped Ga0.25In0.75As/InP heterostructure. Results on samples subjected to the NIL process over a wide range of applied pressure and temperature are presented and discussed. (C) 2003 Elsevier Science B.V. All rights reserved.
5.	Boström, Mathias, et al. (author) Temperature effects on the Casimir attraction between a pair of quantum wells 2000 In: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 51, s. 287-297 Journal article (peer-reviewed)abstract We present calculations of the free energy of attraction between two quantum wells in which the wells are treated as strictly two-dimensional metallic sheets. The van der Waals force exhibits fractional separation dependence in this system. This is in contrast to the usual integer separation dependence. We have performed numerical calculations at different temperatures and with different carrier densities. Except at very low temperatures thermal effects will be a dominating source of attraction. We have determined temperature criteria that must be fulfilled for the fractional separation dependence to be observable. Thermal corrections will be important already at temperatures less than 1 K. We further make some comments on a recent measurement of the Casimir force.
6.	Edholm, Bengt, et al. (author) Electrical investigation of the silicon/diamond interface 1997 In: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 36:1-4, s. 245-248 Journal article (peer-reviewed)abstract A new method for measuring the interface properties, using diamond terminated silicon p-n diodes, is used to quantify the electrical quality and to determine the conduction mechanism of the silicon/diamond interface for two types of diamond. It was found
7.	Edholm, Bengt, et al. (author) Very High Current Gain Enhancement by Substrate Biasing of Lateral Bipolar Transistors on Thin SOI 1993 In: Infos. - : Elsevier BV. ; 22:1-4, s. 379-382 Conference paper (peer-reviewed)
8.	Ewert, Tony, et al. (author) Investigation of the electrical behavior of an asymmetric MOSFET 2003 In: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 65:4, s. 428-438 Journal article (peer-reviewed)abstract In this study a possible approach for improving breakdown voltage while maintaining fT for a MOSFET, is presented. In a conventional MOSFET process with LDD the S/D is implanted with a large tilt angle, which gives an asymmetry due to the shadowing effect by the gate. This asymmetry results in a longer drain-LDD region, which in combination with a lower LDD dose, could reduce the electrical field near the drain pinch-off region. A simulation study for different LDD doses and angles has been performed. It is shown that there exist an optimum range of LDD doses where the asymmetric device has higher figure-of-merit, concerning breakdown voltage and cut-off frequency, than the symmetric MOSFET structure.
9.	Gudmundson, Peter, et al. (author) Stresses in thin films and interconnect lines 2002 In: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 60:1-2, s. 17-29 Journal article (peer-reviewed)abstract The mechanical behavior of thin films and interconnect lines is investigated. Firstly, theoretical models of thermal stress evolution in thin films and passivated or unpassivated lines are considered. Secondly, the effect of texture in a copper thin film with a columnar grain structure is studied from a theoretical point of view. The film consists of three different constituents with (111), (100) and randomly oriented texture. Global properties as well as local stress distributions are considered in detail within a thermoelastic framework. The results are in qualitative agreement with available experimental results. Implications with regards to plastic behavior are briefly discussed. Finally, the potential of the curvature measurement technique for experimental stress evaluation in thin films is considered for initially flat and curved substrate/film systems.
10.	Hansson, B. A. M., et al. (author) A liquid-xenon-jet laser-plasma X-ray and EUV source 2000 In: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 53:04-jan, s. 667-670 Journal article (peer-reviewed)abstract We describe a laser-plasma soft-x-ray source based on a cryogenic-xenon liquid-jet target. The source is suitable for extreme ultraviolet (EUV) projection lithography and proximity x-ray lithography (PXL). Absolute calibrated spectra in the 1-2 nm range and uncalibrated spectra in the 9-15 nm range are obtained using a free-standing transmission grating and a CCD-detector.
11.	Heuser, M, et al. (author) Fabrication of wire-MOSFETs on silicon-on-insulator substrate 2002 In: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 61-2, s. 613-618 Journal article (peer-reviewed)abstract This paper describes the simulation and fabrication of N-type wire-MOSFETs with a multigate structure fabricated on silicon-on-insulator (SOI) material. Both simulations as well as experiments show that short channel effects (SCE) can be reduced by decreasing the channel width of the transistors below 100 nm. The triple-sided gate generates principally higher potential barriers in the channel, suppressing punch through effects significantly. (C) 2002 Elsevier Science B.V. All rights reserved.
12.	Juhasz, Robert, et al. (author) Silicon nanofabrication by electron beam lithography and laser-assisted electrochemical size-reduction 2002 In: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 61-62, s. 563-568 Journal article (peer-reviewed)abstract Laser-assisted electrochemical size-reduction has been carried out on silicon nanostructures produced by electron beam lithography and reactive ion etching. We demonstrate the ability to reduce nanopillars down to 10 nm diameter while preserving shape, but also the possibility of preferential etching of different parts of the pillar by varying the applied bias voltage. Furthermore, the origin of the carriers responsible for the etching is discussed, and we note the presence of a 'dark' etching mechanism working in parallel with the normal dissolution reaction. Finally, the etching of shallow Si dots on a Si surface shows further localization of etching, with a different etching reaction taking place in the vicinity of the structures as opposed to the planar surface, far from the structures.
13.	Korkishko, Y. N., et al. (author) Proton exchanged LiNbO3 and LiTaO3 optical waveguides and integrated optic devices 2003 In: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 69:04-feb, s. 228-236 Journal article (peer-reviewed)abstract We show that proton exchanged LiNbO3 waveguides exhibit very complex structural chemistry. Seven HxLi1-xNbO3 and six HxLi1-xTaO3 crystallographic phases have been identified in PE LiNbO3 and LiTaO3 waveguides, respectively. A correlation is done between the electrooptical, nonlinear and photorefractive properties, the processing conditions and the refractive index changes of the waveguides. Some integrated optical devices have been realized.
14.	Lee, S. K., et al. (author) Low resistivity ohmic contacts on 4H-silicon carbide for high power and high temperature device applications 2002 In: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 60:1-2, s. 261-268 Journal article (peer-reviewed)abstract We investigated titanium based ohmic contacts using co-evaporated epitaxial titanium carbide (TiC) on highly doped n(+)- and p(+)-type epilayers as well as Al ion implanted layers for high power and high temperature device application. Epitaxially grown TiC ohmic contacts on epilayers as well as Al implanted layers of 4H-SiC were formed by UHV co-evaporation with Ti and C-60 at low substrate temperature. The specific contact resistance (rho(C)) was as low as 5 x 10(-6), 2 x 10(-5), and 2 x 10(-5) Omegacm(2) for TiC contacts on n(+), on p(+) epilayer, and on Al implanted layer, respectively, using a linear TLM measurement. In addition to TiC, we also investigated TiW (weight ratio 30:70) ohmic contacts to p- and n-type 4H-SiC for the purpose of long-term reliability tests at high temperature. The average rho(C) of sputtered TiW contacts was 4 x 10(-5) for p(+) and n(+) epilayer. We also found that an evaporated top layer (Au or Pt) helps to protect from degradation of the contacts under long-term reliability tests with temperatures of up to 600degreesC in a vacuum chamber.
15.	Lemme, Max C., 1970-, et al. (author) Influence of channel width on n- and p-type nano-wire-MOSFETs on silicon on insulator substrate 2003 In: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 67-8, s. 810-817 Journal article (peer-reviewed)abstract The fabrication and characterization of nanoscale n- and p-type multi-wire metal-oxide semiconductor field effect transistors (MOSFETs) with a triple gate structure on silicon-on-insulator material (SOI) is described in this paper. Experimental results are compared to simulation with special emphasis on the influence of channel width on the subthreshold behavior. Experiment and simulation show that the threshold voltage depends strongly on the wire width at dimensions below 100 urn. It is further shown that the transition from partial to full channel depletion is dependent on channel geometry. Finally, an increased on-current per chip area is demonstrated for triple-gate SOI MOSFETs compared to planar SOI devices. (C) 2003 Elsevier Science B.V. All rights reserved.
16.	Lundqvist, N., et al. (author) Effects of substrate bias and temperature during titanium sputter-deposition on the phase formation in TiSi2 2002 In: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 60:02-jan, s. 211-220 Journal article (peer-reviewed)abstract The formation of titanium disilicide (TiSi2,) from Ti deposited using ionized metal plasma under different deposition conditions has been investigated. It is shown that deposition at elevated substrate temperature (450degreesC) enhances the formation of the low-resistivity C54 TiSi2, especially in patterned narrow lines. Grain-boundary footprint pictures obtained by atomic force microscopy indicate a larger grain-size distribution for the films deposited at higher substrate temperature. Deposition under substrate bias resulted in reduced contact resistivity. However, the use of substrate bias results in increased probability of bridging of silicide over the isolating spacers.
17.	Marcinkevicius, Saulius, et al. (author) Carrier capture and relaxation in quantum dot structures with different dot densities 2000 In: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; feb-51, s. 79-83 Journal article (peer-reviewed)abstract Carrier dynamics has been measured by time-resolved photoluminescence in self-assembled InGaAs/GaAs quantum dot structures with dot density of the order of 10(8) to 10(10) cm(2). The time of carrier transfer into a dot, which is in the region from 2 to 20 PS, has been found to decrease with increasing quantum dot density. The temperature and photoexcited carrier density dependencies of the carrier transfer times suggest that potential barriers at the barrier, wetting layer and quantum dot interfaces hinder carrier capture in low-density quantum dot structures.
18.	Persson, S., et al. (author) Buffer design and insertion for global interconnections in 0.1 mu m technology 2001 In: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 55:04-jan, s. 19-28 Journal article (peer-reviewed)abstract This paper examines high-speed interconnection design in 0.1 mum technology from a simulation and modelling perspective. It is shown that using Cu metallisation in combination with a low-epsilon dielectric can reduce the minimum delay considerably, as compared to using Al metallisation with SiO2 as the inter-metal dielectric. Consequently, the use of Cu and a low-E dielectric leads to substantial saving of the surface area for buffers that are necessary to incorporate in order to maintain the improved performance when scaling down the device dimensions. As regard to buffer design and insertion, it is a good choice to allow the size of the cascaded inverters in each buffer to increase successively, and simultaneously to permit the size-ratio of two consecutive inverters to increase along the signal propagation direction in order to minimise power consumption and delay. Furthermore, in order to save the precious Si surface area, it is preferable not to drive an interconnection line at a speed unnecessarily higher than the specified speed. Therefore, in parallel with the search for better conductors and insulators as well as improved interconnection technologies, there is an urgent need to address the interconnection issue from the circuit design perspective.
19.	Zhang, Shi-Li (author) Nickel-based contact metallization for SiGe MOSFETs : progress and challenges 2003 In: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 70:04-feb, s. 174-185 Journal article (peer-reviewed)abstract The Ni-based self-aligned silicide process has attracted a rapidly growing interest for contact metallization in Si technology, as the device dimensions are scaled down into the sub-100 nm regime. Incorporation of Ge in the electrodes of a MOSFET, i.e. gate and source/drain, in order to further enhance device performance, has made the study of Ni-Si1-xGex interactions a scientifically and technologically important issue. Among the different germanosilicides of Ni, NiSi1-uGeu (i.e. mono-germanosilicide, with u possibly different from x in the Si1 -xGex) is the most desirable phase due to its low specific resistivity of 12-25 muOmegacm. The focus of the present work is placed on issues concerning the phase and morphology stability of NiSi1-uGeu on single-crystal and polycrystalline Si1-xGex substrates. The related experimental data from our recent work are analysed with reference to two classics on the formation of silicides by d'Heurle [J. Mater. Res. 3 (1988) 167] and by d'Heurle and Gas [J. Mater. Res. 1 (1986) 205]. Influences of C and Pt on the stability of NiSi1-uGeu are also covered. The electrical properties of the NiSi1-uGeu-Si1-xGex contact are discussed referring to our latest experimental results.
20.	Zhou, J., et al. (author) Self-excited piezoelectric microcantilever for gas detection 2003 In: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 69:1, s. 37-46 Journal article (peer-reviewed)abstract Design, fabrication and results from theoretical and experimental studies on the self-excited piezoelectric microcantilever are presented in this paper. Theoretical studies have been carried out to design the microcantilever and have been extended to harmonic analysis using the finite element technique. Silicon microfabrication has been successfully completed to create microcantilever devices. Experimental studies have been performed to obtain the resonance frequencies. Applied as a mass-sensitive sensor, the microcantilever has a sensitivity of - 0.0024%/ppm and a minimum mass loading of 3.5 x 10(-9) g with the help of a zeolite sensitive layer to freon.
21.	Abermann, S., et al. (author) Processing and evaluation of metal gate/high-k/Si capacitors incorporating Al, Ni, TiN, and Mo as metal gate, and ZrO2 and HfO2 as high-k dielectric 2007 In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 84:5-8, s. 1635-1638 Journal article (peer-reviewed)abstract We evaluate various metal gate/high-k/Si capacitors by their resulting electrical characteristics. Therefore, we process MOS gate stacks incorporating aluminium (Al), nickel (Ni), titanium-nitride (TiN), and molybdenum (Mo) as the gate material, and metal organic chemical vapour deposited (MOCVD) ZrO2 and HfO2 as the gate dielectric, respectively. The influence of the processing sequence - especially of the thermal annealing treatment - on the electrical characteristics of the various gate stacks is being investigated. Whereas post metallization annealing in forming gas atmosphere improves capacitance-voltage behaviour (due to reduced interface-, and oxide charge density), current-voltage characteristics degrade due to a higher leakage current after thermal treatment at higher temperatures. The Flatband-voltage values for the TiN-, Mo-, and Ni-capacitors indicate mid-gap pinning of the metal gates, however, Ni seems to be thermally unstable on ZrO2, at least within the process scheme we applied.
22.	Abermann, S., et al. (author) Processing and evaluation of metal gate/high-kappa/Si capacitors incorporating Al, Ni, TiN, and Mo as metal gate, and ZrO2 and HfO2 as high-kappa dielectric 2007 In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 84:5-8, s. 1635-1638 Journal article (peer-reviewed)abstract We evaluate various metal gate/high-K/Si capacitors by their resulting electrical characteristics. Therefore, we process MOS gate stacks incorporating aluminium (Al), nickel (Ni), titanium-nitride (TiN), and molybdenum (Mo) as the gate material, and metal organic chemical vapour deposited (MOCVD) ZrO2 and HfO2 as the gate dielectric, respectively. The influence of the processing sequence - especially of the thermal annealing treatment - on the electrical characteristics of the various gate stacks is being investigated. Whereas post metallization annealing in forming gas atmosphere improves capacitance-voltage behaviour (due to reduced interface-, and oxide charge density), current-voltage characteristics degrade due to a higher leakage current after thermal treatment at higher temperatures. The Flatband-voltage values for the TiN-, Mo-, and Ni-capacitors indicate mid-gap pinning of the metal gates, however, Ni seems to be thermally unstable on ZrO2, at least within the process scheme we applied.
23.	Astromskas, Gvidas, et al. (author) Temperature and frequency characterization of InAs nanowire and HfO2 interface using capacitance-voltage method 2011 In: Microelectronic Engineering. - : Elsevier BV. - 1873-5568 .- 0167-9317. ; 88:4, s. 444-447 Conference paper (peer-reviewed)abstract InAs/HfO2 nanowire capacitors using capacitance-voltage (CV) measurements are investigated in the range of 10 kHz to 10 MHz. The capacitors are based on vertical nanowire arrays that are coated with an 8 nm-thick HfO2 layer by atomic layer deposition. CV characteristics are measured at temperatures in the range between -140 and 40 degrees C and the CV characteristics for nanowires with different Sn and Se n-type doping levels are compared. The comparison of the data at various doping levels points towards large number of traps for highly doped samples, caused by the preferential dopant precursor incorporation at the nanowire surface. We also evaluate the frequency dispersion of the accumulation capacitance and determine values below 2% with weak temperature dependence, indicating the existence of border traps in these nanowire capacitors. (C) 2010 Elsevier B.V. All rights reserved.
24.	Auzelyte, Vaida, et al. (author) Exposure parameters for MeV proton beam writing on SU-8 2006 In: Microelectronic Engineering. - : Elsevier BV. - 1873-5568 .- 0167-9317. ; 83:10, s. 2015-2020 Journal article (peer-reviewed)abstract Proton beam writing was performed on a lithographic resist to determine the main parameters required to achieve the minimum feature size, maximum pattern lateral density and maximum aspect ratio. A 2.5 MeV proton beam focused to sizes between 1.5 and 2.5 mu m was used to expose SU-8 negative resist. The number of protons per pixel was varied in the exposure of SU-8 with thicknesses between 5 and 95 pm. Patterns consisting of single pixels, single-pixel lines and multi-pixel areas with different densities were fabricated. The smallest structures achieved were posts 1.5 pin in diameter with 4:1 structure-space ratio in 15 pm thick resist and the highest aspect ratio structures of 20:1 in 40 pm resist were produced. It was found that the minimum feature size depended only on the beam size, and +/- 10% post size accuracy could be achieved within 40-70% variation of the number of protons. MeV proton beam allows a direct fabrication of complex shapes without a mask in single-step irradiation and. in addition, no proximity correction is needed. We present examples of MeV proton beam written single and multi-pixel microstructures with easily reproducible high aspect ratios and densities. (c) 2006 Elsevier B.V. All rights reserved.
25.	Baus, M, et al. (author) Fabrication of monolithic bidirectional switch devices 2004 In: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 73-4, s. 463-467 Journal article (peer-reviewed)abstract The fabrication scheme of a novel MOS-based power device, a monolithic bidirectional switch (MBS), is presented. This concept allows the integration of a bidirectional switch with the advantages of low power consumption, small package size, and low fabrication costs. Furthermore, device simulations predict a performance benefit for power applications such as matrix converters. In an MBS, the field effect is used to control carrier concentrations in elevated structures made up of nearly intrinsic silicon. A CMOS-compatible nano-fabrication process for the MBS is proposed, employing local oxidation of silicon for self-aligned contact formation. First electrical results are presented. (C) 2004 Elsevier B.V. All rights reserved.
26.	Carlberg, Patrick, et al. (author) Nanoimprint in PDMS on glass with two-level hybrid stamp 2008 In: Microelectronic Engineering. - : Elsevier BV. - 1873-5568 .- 0167-9317. ; 85:1, s. 210-213 Journal article (peer-reviewed)
27.	Chen, Xi, et al. (author) Aged hydrogen silsesquioxane for sub-10 nm line patterns 2016 In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 163, s. 105-109 Journal article (peer-reviewed)abstract Hydrogen silsesquioxane (HSQ) has been used as a negative tone resist in electron beam lithography to define sub-10 nm patterns. The spontaneous polymerization in HSQ usually called aging in this context, sets a restricted period of time for a vendor-warranted use in patterning such small features with satisfactory line-edge roughness (LER). Here, we study the effect of HSQ aging on sensitivity and LER by focusing on exposing line patterns of 10 nm width in various structures. The results show that the 10 nm lines are easily achievable and the LER of the patterned lines remains unaltered even with HSQ that is stored 10 months beyond the vendor-specified expiration date. However, an increasingly pronounced decrease with time of the threshold electron dose (D-th), below which the line width would become less than 10 nm, is observed. After the HSQ expiration for 10 months, the 10 nm lines can be manufactured by reducing D-th to a level that is technically manageable with safe margins. In addition, the inclusion of a prebaldng step at 220 degrees C to accelerate the aging process results in a further reduced D-th for the 10 nm lines and thereby leads to a shortened writing time. The time variation of D-th with respect to the vendor-specified production date of HSQ is found to follow an exponential function of time and can be associated to the classical nucleation-growth polymerization process in HSQ.
28.	Chubarova, Elena, et al. (author) Platinum zone plates for hard X-ray applications 2011 In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 88:10, s. 3123-3126 Journal article (peer-reviewed)abstract We describe the fabrication and evaluation of platinum zone plates for 5–12 kV X-ray imaging and focusing. These nano-scale circular periodic structures are fabricated by filling an e-beam generated mold with Pt in an electroplating process. The plating recipe is described. The resulting zone plates, having outer zone widths of 100 and 50 nm, show good uniformity and high aspect ratio. Their diffraction efficiencies are 50–70% of the theoretical, as measured at the European Synchrotron Radiation Facility. Platinum shows promise to become an attractive alternative to present hard X-ray zone plate materials due to its nano-structuring properties and the potential for zone-plate operation at higher temperatures.
29.	Collaert, N., et al. (author) Ultimate nano-electronics : New materials and device concepts for scaling nano-electronics beyond the Si roadmap 2015 In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 132, s. 218-225 Journal article (peer-reviewed)abstract Abstract In this work, we will give an overview of the innovations in materials and new device concepts that will be needed to continue Moore’s law to the sub-10 nm technology nodes. To meet the power and performance requirements high mobility materials in combination with new device concepts like tunnel FETs and gate-all-around devices will need to be introduced. As the density is further increased and it becomes increasingly difficult to put contacts, spacers and gate in the available gate pitch, disruptive integration schemes such as vertical transistors and monolithic 3D integration might lead the way to the ultimate scaling of CMOS.
30.	Efavi, J K, et al. (author) Investigation of NiAlN as gate-material for submicron CMOS technology 2004 In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 76:1-4, s. 354-359 Journal article (peer-reviewed)abstract Nickel-Aluminium-Nitride (NiAlN) is investigated as gate material for submicron CMOS technology for the first time. The MAIN films have been reactively sputtered from a Ni0.5Al0.5 target in a mixture of argon and nitrogen gas. The influence of the reactive gas content and process temperatures on the work function is presented. Electrical properties are extracted from high and low frequency capacitance-voltage measurements (QSCV, HFCV). Resistivity measurements are shown for various process conditions. Interface properties are observed by transmission electron microscopy. Primarily results show NiAlN's suitability for use as gate material in a CMOS replacement gate technology. Fabrication of n-type metal-oxide-semiconductor field effect transistors with a MAIN gates activated at 900 degreesC is demonstrated.
31.	Fornell, Anna, et al. (author) Optimisation of the droplet split design for high acoustic particle enrichment in droplet microfluidics 2020 In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 226 Journal article (peer-reviewed)abstract We have characterised three droplet split designs for acoustic particle enrichment in water-in-oil droplets. The microfluidic channel design included a droplet generation junction, acoustic focusing channel and a trident-shaped droplet split. The microfluidic channels were dry-etched in silicon and sealed with glass lids by anodic bonding. To each microfluidic chip a piezoelectric transducer was glued, and at actuation of the transducer at the fundamental resonance frequency of the acoustic focusing channel (1.91–1.93 MHz), a half wavelength standing wave field was created between the channel walls. The acoustic force focused the encapsulated particles (3.2 μm, 4.8 μm and 9.9 μm diameter polystyrene microbeads) to the centre-line of the droplets, and when the droplets reached the droplet split the particles were directed into the centre daughter droplets. The results show that the design of the droplet split and the flow ratio between the centre and side outlet channels are the main factors that affect the particle enrichment and particle recovery in the centre daughter droplets. The highest particle enrichment was achieved in the droplet split design having the smallest centre channel (38 μm wide). Using this microfluidic chip design, we demonstrate up to 16.7-fold enrichment of 9.9 μm diameter polystyrene microbeads in the centre daughter droplets. This is almost three times higher particle enrichment than what has previously been presented using other intra-droplet particle enrichment techniques. Moreover, the acoustic technique is label-free and biocompatible.
32.	Garidis, Konstantinos, et al. (author) Mask roughness impact on extreme UV and 193 nm immersion lithography 2012 In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 98, s. 138-141 Journal article (peer-reviewed)abstract The contribution of mask absorber line edge roughness on printed resist lines is studied for extreme UV and 193 nm immersion lithography. Programmed roughness modules were designed for roughness transfer function evaluation on 88 nm pitch line space patterns. The tested modules were designed applying variations of roughness amplitude and spatial frequency. Power spectral density analysis was performed on top-down SEM images. The effect of frequency roughness filtering by the lithographic optical system was studied with different illumination settings. It was found that, except for the degradation of the aerial image due to the filtering effect, less performing illuminations show an increased deterioration of the aerial image quality and thus contribute further to line edge roughness. A comparison with previous work was completed on different mask architectures and photoresist platforms. Resist performance can attenuate the roughness transfer from mask but at the cost of worse chemical gradient at the edges of the exposed regions.
33.	Godavarthi, Srinivas, et al. (author) Impact of wavelength of UV light and UV cure time on chemical and mechanical properties of PECVD deposited porous ultra low-k films 2013 In: Microelectronic Engineering. - : Elsevier. - 0167-9317 .- 1873-5568. ; 107, s. 134-137 Journal article (peer-reviewed)
34.	Gottlob, H. D. B., et al. (author) Gentle FUSI NiSi metal gate process for high-k dielectric screening 2008 In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 85:10, s. 2019-2021 Journal article (peer-reviewed)abstract In this paper, a process flow well suited for screening of novel high-k dielectrics is presented. In vacuo silicon capping of the dielectrics excludes process and handling induced influences especially if hygroscopic materials are investigated. A gentle, low thermal budget process is demonstrated to form metal gate electrodes by turning the silicon capping into a fully silicided nickel silicide. This process enables the investigation of rare earth oxide based high-k dielectrics and specifically their intrinsic material properties using metal oxide semiconductor (MOS) capacitors. We demonstrate the formation of nickel monosilicide electrodes which show smooth interfaces to the lanthanum- and gadolinium-based high-k oxide films. The dielectrics have equivalent oxide thicknesses of EOT = 0.95 nm (lanthanum silicate) and EOT = 0.6 nm (epitaxial gadolinium oxide).
35.	Gottlob, H. D. B., et al. (author) Scaling potential and MOSFET integration of thermally stable Gd silicate dielectrics 2009 In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 86:7-9, s. 1642-1645 Journal article (peer-reviewed)abstract We investigate the potential of gadolinium silicate (GdSiO) as a thermally stable high-k gate dielectric in a gate first integration scheme. There silicon diffuses into gadolinium oxide (Gd2O3) from a silicon oxide (SiO2) interlayer specifically prepared for this purpose. We report on the scaling potential based on detailed material analysis. Gate leakage current densities and EOT values are compatible with an ITRS requirement for low stand by power (LSTP). The applicability of this GdSiO process is demonstrated by fully functional silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). (C) 2009 Elsevier B.V. All rights reserved.
36.	Graczyk, Mariusz, et al. (author) Fabrication of bottle-shaped nanochannels in fused silica using a self-closing effect 2012 In: Microelectronic Engineering. - : Elsevier BV. - 1873-5568 .- 0167-9317. ; 97, s. 173-176 Journal article (peer-reviewed)abstract The spatial control of molecular motor function, using nanostructured surfaces, is of great interest for the development of commercial devices for diagnostics and high-throughput drug screening with molecular motors as targets. In the present study we have fabricated 100-300 nm wide nanochannels, completely subsurfaced on fused silica chips, with the aim to interface them with a microfluidic system. Such a system will allow for changes in the chemical environment surrounding molecular motors, with minimal influence on their directional motion. This will be achieved by changing the chemical environment in a perpendicular direction to the motor motion and allowing the chemical substances to diffuse in and out of the nanochannels via a small slit (5-10 nm) on the top of the nanochannels. To create this slit, and to control its width, we here demonstrate the use of a self-closing effect based on the volume increase (2.27 times) during oxidation of silicon. The details of the fabrication steps (EBL, RIE and oxidation) are discussed. (C) 2012 Elsevier B.V. All rights reserved.
37.	Holmberg, Anders, et al. (author) Nano-fabrication of condenser and micro zone plates for compact X-ray microscopy 2004 In: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 73/74, s. 639-643 Journal article (peer-reviewed)abstract We demonstrate nano-fabrication of high-aspect ratio and high-spatial frequency diffractive X-ray optics with high uniformity for use in a laser-plasma-based compact water-window X-ray microscope. The structures are fabricated on 50 nm thin Si3N4-membranes using a three-layer resist scheme and 30 keV e-beam lithography in combination with reactive ion etching and nickel electroplating. The process is developed on solely commercially available resists and instruments. As examples, we demonstrate fabrication of micro-zone plates with outermost linewidths of 30 nm and an uniform zone height of 160 nm, and a 4.5 mm diameter condenser zone plate with 50-60 nm lines, fabricated by using stitched fields.
38.	Hållstedt, Julius, et al. (author) A robust spacer gate process for deca-nanometer high-frequency MOSFETs 2006 In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 83:3, s. 434-439 Journal article (peer-reviewed)abstract This paper, presents a robust spacer technology for definition of deca-nanometer gate length MOSFETs. Conformal deposition, selective anisotropic dry-etching and selective removal of sacrificial layers enabled patterning of an oxide hard mask with deca-nanometer lines combined with structures defined with I-line lithography on a wafer. The spacer gate technology produces negligible topographies on the hard mask and no residual particles could be detected on the wafer. The line-width roughness of 40 nm poly-Si gate lines was 4 nm and the conductance of 200 pm long lines exhibited a standard deviation of 6% across a wafer. nMOSFETs with 45 nm gate length exhibited controlled short-channel effects and the average maximum transconductance in saturation was 449 mu S/mu m with a standard deviation of 3.7% across a wafer. The devices exhibited a cut-off frequency above 100 GHz at a drain current of 315 mu A/mu m. The physical and electrical results show that the employed spacer gate technology is robust and can define deca-nanometer nMOSFETs with high yield and good uniformity.
39.	Jafri, S Hassan M, et al. (author) Control of junction resistances in molecular electronic devices fabricated by FIB 2011 In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 88:8, s. 2629-2631 Journal article (peer-reviewed)abstract A major hurdle to realize molecular electronic devices (MEDs) is to make reliable electrical contacts to a single or a few molecules. Our nano-contact platform with a gap size of less than 25 nm with resistances above 1000 TΩ was built using combined techniques of photolithography, electron beam lithography and focused ion beam milling. In this study, we have used gold nanoparticles (AuNPs) to bridge the nanoelectrode gaps by dielectrophoretic trapping and thus obtain electrical contacts. The electrodes and/or the nanoparticles were functionalised with 1–2 nm long alkane-thiol molecules so that the electronic structure of these molecules determines the properties of the electrical junction. Molecules were introduced both by functionalising the nanogap and the nanoparticles and the results of both functionalisation protocols are compared. Here, we show the nanogap–nanoparticle bridge set-up containing metal–molecule junctions that can be used as a base for the development of molecular electronics containing only a few molecules under ambient conditions. Current–voltage (I–V) characterization of alkanethiol/gold junction showed non-linear response where mean geometric resistance of four different junctions could be tuned from 20 GΩ to 20 TΩ. The results from the measurements on 1-alkanethiol in such devices is a first step to demonstrate that this platform has the potential to obtain stable electronic devices having relatively small numbers of molecules with reliable metal molecule junction by combing top-down and bottom-up approaches.
40.	Jayakumar, Ganesh, et al. (author) Utilizing the superior etch stop quality of HfO 2 in the front end of line wafer scale integration of silicon nanowire biosensors 2019 In: Microelectronic Engineering. - : Elsevier B.V.. - 0167-9317 .- 1873-5568. ; 212, s. 13-20 Journal article (peer-reviewed)abstract Silicon nanowire (SiNW) biosensors have received a special attention from the research community due to its ability to detect a range of species. The nano feature size of the SiNW has been exploited to fabricate small, low-cost, robust, portable, real-time read-out biosensors. These sensors are manufactured by two methods – top-down or bottom-up. Instead of the bottom-up method, the top-down approach is widely used due to its compatibility with complementary metal-oxide semiconductor (CMOS) process and scope of mass production. However, in the top-down method, the post fabrication microfluidic channel integration to access the SiNW test site remains complex and challenging. Since the nanosensor is expected to operate in a bio environment, it is essential to passivate the metal electrodes while pathways have to be made to access the test site. In this paper, we present a relatively easier method to access the SiNW test site without employing complex microfluidic channels while achieving leakage free passivation of metal electrodes and preserving the integrity of the nanosensor. This is accomplished in the last step of the manufacturing process by employing a lithography mask and reactive ion etching (RIE). HfO 2 integrated crystalline silicon nanosensors are manufactured using novel top-down front end of line (FEOL) sidewall transfer lithography (STL) process. HfO 2 acts as an etch stop layer while performing RIE in the last step to access the sensor test site. The 100 mm wafer scale results of 20 nm × 60 nm × 6 μm (H x W x L) p-type nanosensors shows an average I on /I off ≥ 10 5 with maximum turn-on voltage of −4 V and uniform subthreshold slope of 70 mV/dec. In comparison with sensors encapsulated with SiO 2 , the HfO 2 integrated nanosensors were found to improve the threshold voltage variation by 50%. Based on this work, the HfO 2 integrated SiNW demonstrates good stability for biosensing application.
41.	Jogi, Indrek, et al. (author) Atomic layer deposition of high capacitance density Ta2O5-ZrO2 based dielectrics for metal-insulator-metal structures 2010 In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 87:2, s. 144-149 Journal article (peer-reviewed)abstract We have investigated electrical properties of laminated atomic layer deposited films: ZrO2-Ta2O5, ZrO2-Nb2O5-Ta2O5, ZrO2-TaxNb1-xO5 and Ta2O5-ZrxNbyOz. Even though the capacitances of laminates were often higher compared to films of constituent materials with similar thickness, considerably higher charge storage factors, Q were achieved only when tetragonal ZrO2 was stabilized in ZrO2-Ta2O5 laminate and when the laminate thickness exceeded 50 rim. The decreased Q values in the case of most laminates were the result of increased leakage currents. In the case of thinner films only Ta2O5-ZrxNbyOz, stack possessed capacitance density and Q value higher than reference HfO2. Concerning the conduction mechanisms, in the case of thinner films, the Ta2O5 or TaxNb1-xO5 apparently controlled the leakage either by Richardson-Schottky emission or Poole-Frenkel effect. (C) 2009 Elsevier B.V. All rights reserved
42.	Johansson, Sofia, et al. (author) Temperature and annealing effects on InAs nanowire MOSFETs 2011 In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 88:7, s. 1105-1108 Conference paper (peer-reviewed)abstract We report on temperature dependence on the drive current as well as long-term effects of annealing in vertical InAs nanowire Field-Effect Transistors. Negatively charged traps in the HfO2 gate dielectric are suggested as one major factor in explaining the effects observed in the transistor characteristics. An energy barrier may be correlated with an un-gated InAs nanowire region covered with HfO2 and the effects of annealing may be explained by changed charging on defects in the oxide. Initial simulations confirm the general effects on the I-V characteristics by including fixed charge. (c) 2011 Elsevier B.V. All rights reserved.
43.	Kallesoe, Christian, et al. (author) Selective etching of III-V nanowires for molecular junctions 2008 In: Microelectronic Engineering. - : Elsevier BV. - 1873-5568 .- 0167-9317. ; 85:5-6, s. 1179-1181 Journal article (peer-reviewed)abstract Selective etching of heterostructure III-V nanowires can be used to form tips and narrow gaps simultaneously on multiple nanowires on a single wafer. In this study we tested bromine based etching of gallium arsenide segments in gallium phosphide nanowires. Depending on the etchant and etching conditions, a variety of gap topologies and tip-like structures were observed. The method is compatible with wafer-scale integration of molecular electronics within existing silicon technology, offering control of materials composition, morphology and electronic band gap of the electrodes that can be made so small they might be used as contact electrodes for individual molecules. (C) 2008 Elsevier B.V. All rights reserved.
44.	Karlsson, Mikael, et al. (author) Fabrication of sub-micron high aspect ratio diamond structures with nanoimprint lithography 2010 In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 87:11, s. 2077-2080 Journal article (peer-reviewed)abstract Polycrystalline diamond with optical quality has been patterned using nanoimprint lithography. Nanoimprint lithography is a rather new method for fabrication of resist structures with features sizes down to at least 20 nm. The pattern used in this article is a grating with a period of 600 nm and a fill factor of 0.5. Using plasma etching the nanoimprinted grating is etched into a freestanding diamond substrate. We have accomplished the fabrication of 300 nm diamond features with a depth of about 2 mu m, which corresponds to an aspect ratio of 7.
45.	Koliopoulou, S, et al. (author) A Si/SiGe MOSFET utilizing low-temperature wafer bonding 2005 In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 78-79, s. 244-247 Journal article (peer-reviewed)abstract A process scheme for the fabrication of a low temperature SiGe V-groove MOSFET is demonstrated. The transfer and output characteristics show promising results for the device performance. The source/drain resistance and the quality of the gate insulator/SiGe channel must be optimized for device operation improvement.
46.	Koliopoulou, S, et al. (author) Metal nano-floating gate memory devices fabricated at low temperature 2006 In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 83:4-9, s. 1563-1566 Journal article (peer-reviewed)abstract In this communication, we report on the realization of low-temperature processed Electrically Erasable Programmable Read-Only Memory (EEPROM) like device with embedded gold nanoparticles. The realization is based on the fabrication of a V-groove SiGe Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the functionalization of a gate oxide followed by self-assembly of gold nanoparticles and finally, the deposition of an organic insulator by Langmuir-Blodgett (LB) technique. Such structures were processed at a temperature lower than 400 degrees C. The electrical characteristics of the final hybrid Metal Insulator Semiconductor FET (MISFET) memory cells were evaluated in terms of memory window and program/erase voltage pulses. A model describing the memory characteristics, based on the electronic properties of the gate stack materials, is presented.
47.	Kukli, K., et al. (author) Atomic layer deposition of ZrO2 and HfO2 on deep trenched and planar silicon 2007 In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 84:9-10, s. 2010-2013 Journal article (peer-reviewed)abstract Conformal ZrO2 and HfO2 thin films were grown by atomic layer deposition using novel liquid cyclopentadienyl precursors at 300 degrees C or 350 degrees C on planar Si wafers and deep trenched Si with an aspect ratio of 60:1. The crystal growth and phase content in as-deposited films depended on the precursor, film thickness, and the material grown. The structural and electrical behaviour of the films were somewhat precursor-dependent, revealing better insulating properties in the films grown from oxygen-containing precursors. Also the HfO2 films showed lower leakage compared to ZrO2.
48.	Lemme, Max C., 1970-, et al. (author) Highly selective HBr etch process for fabrication of Triple-Gate nano-scale SOI-MOSFETs 2004 In: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 73-74:SI, s. 346-350 Journal article (peer-reviewed)abstract New three-dimensional device concepts are considered necessary for the ultimate scaling of the gate length of metal-oxide-semiconductor field effect transistors (MOSFETs). Both Triple-Gate field effect transistors and FinFETs require a gate etch process with excellent selectivity over the gate oxide material. In this work, a highly selective, anisotropic gate etch process using HBr and O-2 as the reactive gases in an inductively coupled plasma reactive ion etch tool is described. Polysilicon thickness measurements have been taken to calculate etch rate and uniformity. Polysilicon wafers for each experimental condition were given different overetch times and SiO2 losses were plotted against time, with the gradient yielding the SiO2 etch rate. The optimized etch process yields excellent results for nanoscale polysilicon gates.
49.	Lemme, Max C., 1970-, et al. (author) Nanoscale TiN metal gate technology for CMOS integration 2006 In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 83:4-9, s. 1551-1554 Journal article (peer-reviewed)abstract A TiN metal gate technology including essential natiostructuring process steps is investigated. Complex interdependencies of material deposition, nanolithography, nanoscale etching and post fabrication annealing are taken into account. First, a reactive sputter process has been optimized for plasma damage and stoichiometry. Then, a two step etch process that yields both anisotropy and selectivity has been identified. Finally, MOS-capacitors with TiN/SiO2 gate stacks fabricated with this technology have been exposed to rapid thermal annealing steps. TiN/SiO2 interfaces are chemically stable up to 800 degrees C and yield excellent CV and IV characteristics.
50.	Lindblom, Magnus, et al. (author) SU8 plating mold for high aspect-ratio nickel zone plates 2007 In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 84, s. 1136- Journal article (peer-reviewed)abstract Nickel zone plates are fabricated by electrodeposition into a mold with high aspect ratio and narrow line width. This process requires high-mechanical stability of the mold to avoid pattern collapse in the plating bath. In the present paper we demonstrate how SU-8 can be used as plating mold material in a tri-layer resist to fabricate 35-nm half-pitch nickel gratings with an aspect ratio exceeding 11:1. To attain sufficient stability of the mold the SU-8 was cured by e-beam exposure with a dose of 25 mC/cm2 at 5-keV electron energy.

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