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  • Schenk, A., et al. (author)
  • The impact of hetero-junction and oxide-interface traps on the performance of InAs/Si and InAs/GaAsSb nanowire tunnel FETs
  • 2017
  • In: 2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017. - 9784863486102 ; 2017-September, s. 273-276
  • Conference paper (peer-reviewed)abstract
    • Fabricated InAs/Si and InAs/GaAsSb vertical nanowire tunnel FETs are analyzed by physics-based TCAD with emphasis on the impact of hetero-junction and oxide-interface traps on their performance. After careful fitting of a minimum set of parameters, the effects of diameter scaling and gate alignment are predicted. Trap-assisted tunneling at the oxide interface is suppressed by scaling the diameter into the volume-inversion regime. Gate alignment steepens the slope and increases the ON-current. The 'trap-tolerant' device geometry can result in a small sub-threshold swing despite commonly present trap concentrations.
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Type of publication
conference paper (1)
Type of content
peer-reviewed (1)
Author/Editor
Schenk, A (1)
Wernersson, L. E. (1)
Memisevic, E. (1)
Sant, S. (1)
Moselund, K. (1)
Riel, H. (1)
University
Lund University (1)
Language
English (1)
Research subject (UKÄ/SCB)
Engineering and Technology (1)
Year
2017 (1)

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