SwePub - search: WFRF:(Börjeson Erik 1984)

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1.	Börjeson, Erik, 1984, et al. (author) ASIC Design Exploration of Phase Recovery Algorithms for M-QAM Fiber-Optic Systems 2019 In: Optics InfoBase Conference Papers. - 2162-2701. - 9781943580538 Conference paper (peer-reviewed)abstract We develop circuit implementations and explore design optimizations for one blind and one pilot-based carrier phase-recovery algorithm, where the former algorithm is shown to dissipate 1.8-4.5 pJ/bit and the latter 0.5-0.3 pJ/bit, using 16 to 256QAM.
2.	Börjeson, Erik, 1984, et al. (author) Benchmarking of Carrier Phase Recovery Circuits for M-QAM Coherent Systems 2021 In: Optical Fiber Communication Conference, OFC 2021. - 9781943580866 - 9781557528209 Conference paper (peer-reviewed)abstract We benchmark blind carrier phase recovery DSP circuits in terms of SNR penalty, power dissipation, latency, area usage, and cycle slip probability, to identify optimal implementations for 16, 64, and 256QAM.
3.	Börjeson, Erik, 1984, et al. (author) Circuit Implementation of Pilot-Based Dynamic MIMO Equalization for Coupled-Core Fibers 2024 In: Optical Fiber Communication Conference, OFC 2024. - 9781957171326 Conference paper (peer-reviewed)abstract We explore ASIC implementation for pilot-based MIMO equalizers for coupled-core transmission, considering chip area scaling trends and performance impact of time-dependent drift. For a system with 28-GBd subcarriers, an equalizer for 8 × 8 is 5.3 times larger than for 2 × 2.
4.	Börjeson, Erik, 1984, et al. (author) Cycle-Slip Rate Analysis of Blind Phase Search DSP Circuit Implementations 2020 In: 2020 Optical Fiber Communications Conference and Exhibition, OFC 2020 - Proceedings. - 9781943580712 Conference paper (peer-reviewed)abstract Using FPGA-accelerated simulations, we study the cycle-slip rate of 16QAM blind phase search implementations. While block averaging suffers from degraded BER when compared to sliding-window averaging, it results in lower cycle-slip rates and power dissipation.
5.	Börjeson, Erik, 1984, et al. (author) Energy-Efficient Implementation of Carrier Phase Recovery for Higher-Order Modulation Formats 2021 In: Journal of Lightwave Technology. - 0733-8724 .- 1558-2213. ; 39:2, s. 505-510 Journal article (peer-reviewed)abstract We introduce circuit implementations of one- and two-stage carrier phase recovery (CPR) for 256QAM coherent optical receivers. We describe in detail the optimizations of algorithms, such as modified Viterbi-Viterbi (mVV), blind phase search (BPS), and principal component-based phase estimation (PCPE), that are required to develop energy-efficient CPR circuits and show how design parameter settings and limited fixed-point resolution affect the SNR penalty. 30-GBaud CPR circuit netlists synthesized in a 22-nm CMOS process technology allow us to study trade-offs between energy per bit and SNR penalty. We show that it is possible to reach an energy dissipation of around 1 pJ/bit at an SNR penalty of 0.6 dB for two-stage PCPE+BPS and mVV+BPS implementations, and that PCPE+BPS is the preferred choice thanks to its smaller area.
6.	Börjeson, Erik, 1984, et al. (author) Fiber-on-Chip: Digital Emulation of Channel Impairments for Real-Time DSP Evaluation 2023 In: Journal of Lightwave Technology. - 0733-8724 .- 1558-2213. ; 41:3, s. 888-896 Journal article (peer-reviewed)abstract We describe the Fiber-on-Chip (FoC) approach to verification of digital signal processing (DSP) circuits, where digital models of a fiber-optic communication system are implemented in the same hardware as the DSP under test. The approach can enable cost-effective long-term DSP evaluations without the need for complex optical-electronic testbeds with high-speed interfaces, shortening verification time and enabling deep bit-error rate evaluations. Our FoC system currently contains a digital model of a transmitter generating a pseudo-random bitstream and a digital model of a channel with additive white Gaussian noise, phase noise and polarization-mode dispersion. In addition, the FoC system contains digital features for real-time control of channel parameters, using low-speed communication interfaces, and for autonomous real-time analysis, which enable us to batch multiple unsupervised emulations on the same hardware. The FoC system can target both field-programmable gate arrays, for fast evaluation of fixed-point logic, and application-specific integrated circuits, for accurate power dissipation measurements.
7.	Börjeson, Erik, 1984 (author) Implementation and Evaluation of Signal Processing Circuits for Optical Communication 2024 Doctoral thesis (other academic/artistic)abstract The digital signal processing (DSP) circuits used in the fiber-optic communication links that make up the backbone of the Internet can be a significant contributor the over-all power dissipation of a link. As the number of connected users and their bandwidth requirements are expected to continue to grow over the coming years, the development of power-efficient high-throughput DSP systems is a critical factor in enabling this growth. Unfortunately, DSP designers can no longer depend on foundries delivering faster and more power-efficient circuits for each new process node, due to both economical and physical limitations. As a result, more stringent speed and power requirements are put on the circuit designs. Carrier phase recovery (CPR) is one subsystem of a typical DSP system for fiber-optic communication. In this thesis, we explore and evaluate circuit designs of multiple types of CPR, with a focus on single-mode systems. The circuit designs allow us to uncover trade-offs between power dissipation, area, throughput and signal degradation, for different types of systems employing a range of modulation formats. Coupled-core multi-mode fiber systems have been suggested as a way to increase throughput by utilizing also the spatial dimension, and this thesis describes a multiple-input multiple-output adaptive equalizer targeting these systems. The equalizer circuit enables exploration of how this critical subsystem scales to higher core counts. Additionally, we describe a circuit verification and evaluation environment that has the potential to speed up simulations by orders of magnitude by emulating a fiber-optic link onboard an application-specific integrated circuit or a field-programmable gate array.
8.	Börjeson, Erik, 1984 (author) Implementation of Carrier Phase Recovery Circuits for Optical Communication 2020 Licentiate thesis (other academic/artistic)abstract Fiber-optic links form a vital part of our increasingly connected world, and as the number of Internet users and the network traffic increases, reducing the power dissipation of these links becomes more important. A considerable part of the total link power is dissipated in the digital signal processing (DSP) subsystems, which show a growing complexity as more advanced modulation formats are introduced. Since DSP designers can no longer take reduced power dissipation with each new CMOS process node for granted, the design of more efficient DSPalgorithms in conjunction with circuit implementation strategies focused on power efficiency is required. One part of the DSP for a coherent fiber-optic link is the carrier phase recovery (CPR) unit, which can account for a significant portion of the DSP power dissipation, especially for shorter links. A wide range of CPR algorithms is available, but reliable estimates of their power efficiency is missing, making accurate comparisons impossible. Furthermore, much of the current literature does not account for the limited precision arithmetic of the DSP. In this thesis, we develop circuit implementations based on a range of suggested CPR algorithms, focusing on power efficiency. These circuits allow us to contrast different CPR solutions based not only on power dissipation, but also on the quality of the phase estimation, including fixed-point arithmetic aspects. We also show how different parameter settings affect the power efficiency and the implementation penalty. Additionally, the thesis includes a description of our field-programmable gate-array fiber-emulation environment, which can be used to study rare phenomena in DSP implementations, or to reach very low bit-error rates. We use this environment to evaluate the cycle-slip probability of a CPR implementation.
9.	Börjeson, Erik, 1984, et al. (author) Multi-Format Carrier Phase Recovery Using a Programmable Circuit 2021 In: Optics InfoBase Conference Papers. Conference paper (peer-reviewed)abstract We introduce an application-specific circuit that can be programmed to efficiently perform blind carrier phase recovery for different modulation formats. A circuit implementation that supports QPSK/16/32/64QAM is evaluated.
10.	Börjeson, Erik, 1984, et al. (author) Real-Time Implementation of Machine-Learning DSP 2024 In: 2024 Optical Fiber Communications Conference and Exhibition, OFC 2024 - Proceedings. Conference paper (peer-reviewed)abstract While ML algorithms can learn and adapt to channel characteristics, implementation of ML-based DSP hardware is challenging. We demonstrate a real-time implementation of a model-based ML equalizer that compensates a non-linear and time-varying channel.
11.	Börjeson, Erik, 1984, et al. (author) Towards FPGA Emulation of Fiber-Optic Channels for Deep-BER Evaluation of DSP Implementations 2019 In: Optics InfoBase Conference Papers. - 2162-2701. ; Part F137-SPPCom 2019 Conference paper (peer-reviewed)abstract We introduce an FPGA-based fiber-optic channel emulator, including both AWGN and carrier phase noise, which can be used to perform deep-BER simulations of DSP implementations and accurately evaluate DSP implementation penalties.
12.	Börjeson, Erik, 1984, et al. (author) VLSI Implementations of Carrier Phase Recovery Algorithms for M-QAM Fiber-Optic Systems 2020 In: Journal of Lightwave Technology. - 0733-8724 .- 1558-2213. ; 38:14, s. 3616-3623 Journal article (peer-reviewed)abstract We present circuit implementations of blind phase search (BPS) carrier phase recovery (CPR) for M-QAM coherent optical receivers and highlight some BPS algorithm modifications necessary to obtain efficient VLSI circuits. In addition, we show how three key design parameters (input word length, number of test phases, and type and size of averaging window) affect the resulting implementation. To study design tradeoffs, we develop BPS CPR circuit netlists for a 32-GBaud system, using a 22-nm CMOS process technology: Our implementations reach energy efficiencies of around 1 pJ/bit for 16QAM up to 3 pJ/bit for 256QAM, at an SNR penalty of approximately 0.25 dB at a BER of 10^(−2). Furthermore, we present a circuit implementation of pilot-symbol-aided CPR, reaching 0.38 pJ/bit and 0.34 pJ/bit for 16QAM and 256QAM, respectively, at a slightly higher SNR penalty. The two CPR methods are also evaluated in terms of silicon area and scaling to higher-order modulation formats.
13.	Fougstedt, Christoffer, 1990, et al. (author) ASIC Design Exploration for DSP and FEC of 400-Gbit/s Coherent Data-Center Interconnect Receivers 2020 In: 2020 Optical Fiber Communications Conference and Exhibition, OFC 2020 - Proceedings. - : Optical Society of America. - 9781943580712 Conference paper (peer-reviewed)abstract We perform exploratory ASIC design of key DSP and FEC units for 400-Gbit/s coherent data-center interconnect receivers. In 22-nm CMOS, the considered units together dissipate 5W, suggesting implementation feasibility in power-constrained form factors.
14.	Kan, Haorui, et al. (author) Digital Emulation of Time-Varying PMD for Real-Time DSP Evaluations 2021 In: Asia Communications and Photonics Conference, ACP. - 2162-108X. - 9781957171005 ; M4H Conference paper (peer-reviewed)abstract We introduce a digital PMD emulator to accelerate BER analysis of coherent receiver DSPs. The emulator creates parameterizable, time-varying impairments, which we use to demonstrate real-time analysis of a CMA equalizer.
15.	Larsson-Edefors, Per, 1967, et al. (author) Fiber-on-Chip: Digital FPGA Emulation of Channel Impairments for Real-Time Evaluation of DSP 2022 In: Optics InfoBase Conference Papers. - 2162-2701. Conference paper (peer-reviewed)abstract We describe the Fiber-on-Chip (FoC) approach, in which digital models are used for real-time emulation of an optical communication system, to achieve cost-effective and reproducible long-term DSP evaluations inside a single chip.
16.	Larsson-Edefors, Per, 1967, et al. (author) Power-Efficient ASIC Implementation of DSP Algorithms for Coherent Optical Communication 2020 In: 2020 IEEE Photonics Society Summer Topical Meeting Series, SUM 2020 - Proceedings. ; July 2020 Conference paper (peer-reviewed)abstract Coherent optical communication critically relies on efficient digital signal processing (DSP). We outline the application-specific integrated circuit (ASIC) implementation flow for DSP algorithms and discuss approaches to reducing the digital ASIC power dissipation of high-throughput DSP implementations for coherent fiber-optic communication systems.
17.	Liu, Keren, et al. (author) FPGA-based Optical Kerr Effect Emulator 2022 In: Optics InfoBase Conference Papers. Conference paper (peer-reviewed)abstract We propose a digital emulator of the optical Kerr effect, suitable for FPGA implementation. In addition, we study a combined PMD and Kerr emulator implementation with respect to DSP hardware aspects such as fixed-point performance.
18.	Liu, Keren, et al. (author) FPGA Implementation of Multi-Layer Machine Learning Equalizer with On-Chip Training 2023 In: 2023 Optical Fiber Communications Conference and Exhibition, OFC 2023 - Proceedings. Conference paper (peer-reviewed)abstract We design and implement an adaptive machine learning equalizer that alternates multiple linear and nonlinear computational layers on an FPGA. On-chip training via gradient backpropagation is shown to allow for real-time adaptation to time-varying channel impairments.
19.	Lundberg, Lars, 1989, et al. (author) Power Consumption Savings Through Joint Carrier Recovery for Spectral and Spatial Superchannels 2018 In: European Conference on Optical Communication, ECOC. ; 2018-September Conference paper (peer-reviewed)abstract The power consumption of a circuit implementation of a master-slave carrier recovery scheme is studied. Slave power consumption is 27% of master power for 16QAM and 13% for 64QAM, enabling power savings approaching 0.7W per channel through joint processing.
20.	Mazur, Mikael, 1990, et al. (author) Coherent Optical Supervisory Channel Enabling Per-Span Real-Time Gigabit/s Transmission and Distributed Sensing 2024 In: European Conference on Optical Communication, ECOC. Conference paper (peer-reviewed)abstract We demonstrate a real-time coherent optical supervisory channel over ≈90 km field fiber in Tokyo, Japan. The data signal is frequency multiplexed with a chirped pulse waveform, enabling distributed acoustic sensing and data transmission with DSP-based integrated link sensing in one device.
21.	Mazur, Mikael, 1990, et al. (author) Continuous Fiber Sensing over Field-Deployed Metro Link using Real-Time Coherent Transceiver and DAS 2022 In: 2022 European Conference on Optical Communication, ECOC 2022. - 9781957171159 Conference paper (peer-reviewed)abstract We use an FPGA-based real-time coherent transceiver prototype with continuous μs-level state-of-polarization readouts and a commercial DAS system to perform fiber sensing. Link monitoring and active detection of link tampering is demonstrated using both systems, showing how SOP-based sensing complements DAS in metro environments.
22.	Mazur, Mikael, 1990, et al. (author) Field Trial of FPGA-Based Real-Time Sensing Transceiver over 524km of Live Aerial Fiber 2023 In: Optical Fiber Communication Conference, OFC 2023. - 9781957171180 Conference paper (peer-reviewed)abstract We perform fiber sensing over a 524 km live network using a real-time coherent transceiver prototype. Polarization and length changes from the link consisting exclusively of aerial fiber wound around high-voltage power cables are continuously monitored.
23.	Mazur, Mikael, 1990, et al. (author) Real-Time MIMO Transmission over Field-Deployed Coupled-Core Multi-Core Fibers 2022 In: 2022 Optical Fiber Communications Conference and Exhibition, OFC 2022 - Proceedings. - 9781943580071 Conference paper (peer-reviewed)abstract We perform parallel continuous measurements of deployed SDM fibers using real-time coherent receivers implemented on FPGAs. Fast readouts enabling real-time tracking of the DSP implementation, showing that coupled-core fibers are compatible with real-time DSP implementations.
24.	Mazur, Mikael, 1990, et al. (author) Real-Time Monitoring of Cable Break in a Live Network using a Coherent Transceiver Prototype 2024 In: Optical Fiber Communication Conference, OFC 2024. - 9781957171326 Conference paper (peer-reviewed)abstract We monitor a 524-km live network link using an real-time FPGA-based sensing-capable transceiver prototype during a human-caused cable break. Polarization sensing data shows minute-level potential break warning precursors, offering outage mitigation prospects.
25.	Mazur, Mikael, et al. (author) Real-Time Transmission over 2x55 km All 7-Core Coupled-Core Multi-Core Fiber Link 2022 In: Optical Fiber Communication Conference, OFC 2022. - 9781557524669 - 9781557528209 Conference paper (peer-reviewed)abstract We demonstrate the first transmission experiment using 7-core coupled-core fiber with in-line coupled-core multi-core amplifiers and real-time DSP. The real-time DSP is implemented using a single FPGA that performs MIMO processing across all 7 cores.
26.	Mazur, Mikael, 1990, et al. (author) SDM transmission Using Real-Time Digital Signal Processing (invited) 2024 In: European Conference on Optical Communication, ECOC. Conference paper (peer-reviewed)
27.	Mazur, Mikael, 1990, et al. (author) Transoceanic Phase and Polarization Fiber Sensing Using Real-Time Coherent Transceiver 2022 In: Optical Fiber Communication Conference, OFC 2022. - 9781557524669 - 9781557528209 Conference paper (peer-reviewed)abstract We implement a real-time coherent transceiver with fast streaming outputs for environmental sensing. Continuous sensing using phase and equalizer outputs over 12800 km of submarine cable enabled time resolved interferometry in broad spectral range of 10 mHz-1 kHz.
28.	Romon Sagredo, Rafael, et al. (author) Waveform Memory for Real-Time FPGA Test of Fiber-Optic Receiver DSPs 2022 In: 2022 IEEE Nordic Circuits and Systems Conference, NORCAS 2022 - Proceedings. Conference paper (peer-reviewed)abstract Verification of advanced circuit implementations poses many challenges. For complex digital signal processing (DSP) circuits, logic simulations may be prohibitively slow when non-stationary scenarios are considered. A real-time emulation technique like the Fiber-on-Chip (FoC) approach can significantly speed up DSP logic verification. However, a potential weakness with this type of emulation is that it does not use data obtained from experiments, but synthetically creates test data. We introduce a waveform memory, which can be integrated with FoC systems and similar emulators, and which allows measured waveforms to be stored and fed to DSP circuits under test. We perform real-time FPGA experiments where we evaluate a carrier-phase recovery (CPR) module that is tested using either waveform data or synthetic data. Our results for the two different data sets show that the CPR module behaves similarly, both qualitatively and quantitatively, which indicates that the synthetic phase-noise model is a valid replacement of measured data.

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