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1.	Khan, U., et al. (author) Large scale programmable photonic circuits using silicon photonic MEMS 2022 In: 2022 Conference on Lasers and Electro-Optics, CLEO 2022. - : Institute of Electrical and Electronics Engineers Inc.. Conference paper (peer-reviewed)abstract We demonstrate low-power and non-volatile MEMS actuators on an industrially established silicon photonics platform. The compact electrostatically actuated phase shifters and tunable couplers enable large-scale programmable photonic integrated circuits.
2.	Bleiker, Simon J., et al. (author) Adhesive Wafer Bonding for Heterogeneous System Integration 2018 In: ECS Meeting Abstracts. Conference paper (peer-reviewed)
3.	Bleiker, Simon J., et al. (author) Device with a waveguide supported on a substrate and method for its fabrication 2020 Patent (pop. science, debate, etc.)abstract ABSTRACT A device (1) and a method for fabricating such a device is described. The device (1) comprises a device layer (4), a substrate (2) defining a substrate plane (3). A device layer plane (5) is defined on the side of the device layer (4) facing the substrate (2). The device also comprises a waveguide (7) for guiding an electromagnetic wave. The waveguide (7) is supported on the substrate (2) via a support structure (6) extending from the substrate (2) to the device layer (4). The ratio of the largest distance (D1), perpendicular to the substrate plane (3), between a free surface of the waveguide (7) facing the substrate and any solid material to the height (h) of the waveguide (7) is more than 6, i.e. D1/h \textgreater 6. The ratio of the distance (D2), perpendicular to the substrate plane (3), between the device layer plane (5) and the substrate plane (3) to the height (h) of the waveguide (7) is more than 6, i.e. D2/h \textgreater 6.
4.	Dubois, Valentin J., et al. (author) Scalable Manufacturing of Nanogaps 2018 In: Advanced Materials. - : Wiley-VCH Verlagsgesellschaft. - 0935-9648 .- 1521-4095. ; 30:46 Research review (peer-reviewed)abstract The ability to manufacture a nanogap in between two electrodes has proven a powerful catalyst for scientific discoveries in nanoscience and molecular electronics. A wide range of bottom-up and top-down methodologies are now available to fabricate nanogaps that are less than 10 nm wide. However, most available techniques involve time-consuming serial processes that are not compatible with large-scale manufacturing of nanogap devices. The scalable manufacturing of sub-10 nm gaps remains a great technological challenge that currently hinders both experimental nanoscience and the prospects for commercial exploitation of nanogap devices. Here, available nanogap fabrication methodologies are reviewed and a detailed comparison of their merits is provided, with special focus on large-scale and reproducible manufacturing of nanogaps. The most promising approaches that could achieve a breakthrough in research and commercial applications are identified. Emerging scalable nanogap manufacturing methodologies will ultimately enable applications with high scientific and societal impact, including high-speed whole genome sequencing, electromechanical computing, and molecular electronics using nanogap electrodes.
5.	Laakso, Miku J., et al. (author) Through-Glass Vias for Glass Interposers and MEMS Packaging Applications Fabricated Using Magnetic Assembly of Microscale Metal Wires 2018 In: IEEE Access. - : Institute of Electrical and Electronics Engineers (IEEE). - 2169-3536. ; 6, s. 44306-44317 Journal article (peer-reviewed)abstract A through-glass via (TGV) provides a vertical electrical connection through a glass substrate. TGVs are used in advanced packaging solutions, such as glass interposers and wafer-level packaging of microelectromechanical systems (MEMS). However, TGVs are challenging to realize because via holes in glass typically do not have a sufficiently high-quality sidewall profile for super-conformal electroplating of metal into the via holes. To overcome this problem, we demonstrate here that the via holes can instead be filled by magnetically assembling metal wires into them. This method was used to produce TGVs with a typical resistance of 64 m Omega, which is comparable with other metal TGV types reported in the literature. In contrast to many TGV designs with a hollow center, the proposed TGVs can be more area efficient by allowing solder bump placement directly on top of the TGVs, which was demonstrated here using solder-paste jetting. The magnetic assembly process can be parallelized using an assembly robot, which was found to provide an opportunity for increased wafer-scale assembly speed. The aforementioned qualities of the magnetically assembled TGVs allow the realization of glass interposers and MEMS packages in different thicknesses without the drawbacks associated with the current TGV fabrication methods.
6.	Ayala, Christopher L., et al. (author) Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts 2015 In: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 113, s. 157-166 Journal article (peer-reviewed)abstract Nanoelectromechanical (NEM) switches have the potential to complement or replace traditional CMOS transistors in the area of ultra-low-power digital electronics. This paper reports the demonstration of prototype circuits including the first 3-stage ring oscillator built using cell-level digital logic elements based on curved NEM switches. The ring oscillator core occupies an area of 30 mu m x 10 mu m using 6 NEM switches. Each NEM switch device has a footprint of 5 mu m x 3 mu m, an air gap of 60 mu m and is coated with amorphous carbon (a-C) for reliable operation. The ring oscillator operates at a frequency of 6.7 MHz, and confirms the simulated inverter propagation delay of 25 ns. The successful fabrication and measurement of this demonstrator are key milestones on the way towards an optimized, scaled technology with sub-nanosecond switching times, lower operating voltages and VLSI implementation.
7.	Bleiker, Simon J., et al. (author) Adhesive wafer bonding with ultra-thin intermediate polymer layers 2017 In: Sensors and Actuators A-Physical. - : Elsevier. - 0924-4247 .- 1873-3069. ; 260, s. 16-23 Journal article (peer-reviewed)abstract Wafer bonding methods with ultra-thin intermediate bonding layers are critically important in heterogeneous 3D integration technologies for many NEMS and photonic device applications. A promising wafer bonding approach for 3D integration is adhesive bonding. So far however, adhesive bonding processes relied on relatively thick intermediate adhesive layers. In this paper, we present an adhesive wafer bonding process using an ultra-thin intermediate adhesive layer with sub-200 nm thickness. We demonstrate adhesive bonding of silicon wafers with a near perfect bonding yield of >99% and achieve less than ±10% non-uniformity of the intermediate layer thickness across an entire 100 mm-diameter wafer. A bond strength of 4.8 MPa was measured for our polymer adhesive, which is considerably higher than previously reported for other ultra-thin film adhesives. Additionally, the adhesive polymer used in the proposed method features excellent chemical and mechanical stability. We also report on a potential strategy for mitigating the formation of micro-voids in the polymer adhesive at the bond interface. Furthermore, the polymer adhesive can be sacrificially removed by oxygen plasma etching for both isotropic and anisotropic release etching. The characteristics of the adhesive wafer bonding process and its compatibility with CMOS wafers, makes it very attractive for heterogeneous 3D integration processes targeted at CMOS-integrated NEMS and photonic devices.
8.	Bleiker, Simon J., et al. (author) Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding 2016 In: Micromachines. - Basel, Switzerland : Multidisciplinary Digital Publishing Institute (MDPI). - 2072-666X. ; 7:10, s. 192- Journal article (peer-reviewed)abstract Device encapsulation and packaging often constitutes a substantial part of the fabrication cost of micro electro-mechanical systems (MEMS) transducers and imaging sensor devices. In this paper, we propose a simple and cost-effective wafer-level capping method that utilizes a limited number of highly standardized process steps as well as low-cost materials. The proposed capping process is based on low-temperature adhesive wafer bonding, which ensures full complementary metal-oxide-semiconductor (CMOS) compatibility. All necessary fabrication steps for the wafer bonding, such as cavity formation and deposition of the adhesive, are performed on the capping substrate. The polymer adhesive is deposited by spray-coating on the capping wafer containing the cavities. Thus, no lithographic patterning of the polymer adhesive is needed, and material waste is minimized. Furthermore, this process does not require any additional fabrication steps on the device wafer, which lowers the process complexity and fabrication costs. We demonstrate the proposed capping method by packaging two different MEMS devices. The two MEMS devices include a vibration sensor and an acceleration switch, which employ two different electrical interconnection schemes. The experimental results show wafer-level capping with excellent bond quality due to the re-flow behavior of the polymer adhesive. No impediment to the functionality of the MEMS devices was observed, which indicates that the encapsulation does not introduce significant tensile nor compressive stresses. Thus, we present a highly versatile, robust, and cost-efficient capping method for components such as MEMS and imaging sensors.
9.	Bleiker, Simon J. (author) Heterogeneous 3D Integration and Packaging Technologies for Nano-Electromechanical Systems 2017 Doctoral thesis (other academic/artistic)abstract Three-dimensional (3D) integration of micro- and nano-electromechanical systems (MEMS/NEMS) with integrated circuits (ICs) is an emerging technology that offers great advantages over conventional state-of-the-art microelectronics. MEMS and NEMS are most commonly employed as sensor and actuator components that enable a vast array of functionalities typically not attainable by conventional ICs. 3D integration of NEMS and ICs also contributes to more compact device footprints, improves device performance, and lowers the power consumption. Therefore, 3D integration of NEMS and ICs has been proposed as a promising solution to the end of Moore’s law, i.e. the slowing advancement of complementary metal-oxide-semiconductor (CMOS) technology.In this Ph.D. thesis, I propose a comprehensive fabrication methodology for heterogeneous 3D integration of NEM devices directly on top of CMOS circuits. In heterogeneous integration, the NEMS and CMOS components are fully or partially fabricated on separate substrates and subsequently merged into one. This enables process flexibility for the NEMS components while maintaining full compatibility with standard CMOS fabrication. The first part of this thesis presents an adhesive wafer bonding method using ultra-thin intermediate bonding layers which is utilized for merging the NEMS components with the CMOS substrate. In the second part, a novel NEM switch concept is introduced and the performance of CMOS-integrated NEM switch circuits for logic and computation applications is discussed. The third part examines two different packaging approaches for integrated MEMS and NEMS devices with either hermetic vacuum cavities or low-cost glass lids for optical applications. Finally, a novel fabrication approach for through silicon vias (TSVs) by magnetic assembly is presented, which is used to establish an electrical connection from the packaged devices to the outside world.
10.	Bleiker, Simon J., et al. (author) High-Aspect-Ratio Through Silicon Vias for High-Frequency Application Fabricated by Magnetic Assembly of Gold-Coated Nickel Wires 2015 In: IEEE Transactions on Components, Packaging, and Manufacturing Technology. - : IEEE Press. - 2156-3950 .- 2156-3985. ; 5:1, s. 21-27 Journal article (peer-reviewed)abstract In this paper, we demonstrate a novel manufacturing technology for high-aspect-ratio vertical interconnects for high-frequency applications. This novel approach is based on magnetic self-assembly of prefabricated nickel wires that are subsequently insulated with a thermosetting polymer. The high-frequency performance of the through silicon vias (TSVs) is enhanced by depositing a gold layer on the outer surface of the nickel wires and by reducing capacitive parasitics through a low-k polymer liner. As compared with conventional TSV designs, this novel concept offers a more compact design and a simpler, potentially more cost-effective manufacturing process. Moreover, this fabrication concept is very versatile and adaptable to many different applications, such as interposer, micro electromechanical systems, or millimeter wave applications. For evaluation purposes, coplanar waveguides with incorporated TSV interconnections were fabricated and characterized. The experimental results reveal a high bandwidth from dc to 86 GHz and an insertion loss of <0.53 dB per single TSV interconnection for frequencies up to 75 GHz.
11.	Bleiker, Simon J., et al. (author) High-speed Metal-filling of Through-Silicon Vias (TSVs) by Parallelized Magnetic Assembly of Micro-Wires 2016 In: 2016 IEEE 29th International Conference on Micro Electro Mechanical Systems (MEMS). - : Institute of Electrical and Electronics Engineers (IEEE). - 9781509019731 ; , s. 577-580 Conference paper (peer-reviewed)abstract This work reports a parallelized magnetic assembly method for scalable and cost-effective through-silicon via (TSV) fabrication. Our fabrication approach achieves high throughput by utilizing multiple magnets below the substrate to assemble TSV structures on many dies in parallel. Experimental results show simultaneous filling of four arrays of TSVs on a single substrate, with 100 via-holes each, in less than 20 seconds. We demonstrate that increasing the degree of parallelization by employing more assembly magnets below the substrate has no negative effect on the TSV filling speed or yield, thus enabling scaled-up TSV fabrication on full wafer-level. This method shows potential for industrial application with an estimated throughput of more than 70 wafers per hour in one single fabrication module. Such a TSV fabrication process could offer shorter processing times as well as higher obtainable aspect ratios compared to conventional TSV filling methods.
12.	Bogaerts, Wim, et al. (author) Scaling programmable silicon photonics circuits 2023 In: Silicon Photonics XVIII. - : SPIE-Intl Soc Optical Eng. Conference paper (peer-reviewed)abstract We give an overview the progress of our work in silicon photonic programmable circuits, covering the techn stack from the photonic chip over the driver electronics, packaging technologies all the way to the sof layers. On the photonic side, we show our recent results in large-scale silicon photonic circuits with diff tuning technologies, including heaters, MEMS and liquid crystals, and their respective electronic driving sch We look into the scaling potential of these different technologies as the number of tunable elements in a ci increases. Finally, we elaborate on the software routines for routing and filter synthesis to enable the pho programmer.
13.	Edinger, Pierre, et al. (author) A vacuum-sealed silicon photonic MEMS tunable ring resonator with independent control over coupling and phase Other publication (other academic/artistic)abstract Ring resonators are a vital element for designing filters, optical delay lines, or sensors in silicon photonics. However, reconfigurable ring resonators with low-power consumption and good optical performance are not available in foundries today. We demonstrate an add-drop ring resonator with the independent tuning of coupling and round-trip phase using low-power microelectromechanical (MEMS) actuation. The MEMS rings are individually vacuum-sealed on wafer scale, enabling reliable long-term operation with low damping. On resonance, we demonstrate a modulation increase of up to 15 dB, with a voltage bias of 4V and a peak drive amplitude as low as 20mV.
14.	Edinger, Pierre, et al. (author) An Integrated Platform for Cavity Optomechanics with Vacuum-Sealed Silicon Photonic MEMS 2023 In: 2023 22nd International Conference on Solid-State Sensors, Actuators and Microsystems, Transducers 2023. - : Institute of Electrical and Electronics Engineers Inc.. ; , s. 425-428 Conference paper (peer-reviewed)abstract Silicon photonics is an excellent platform for integrated cavity optomechanics due to silicon's high light confinement and favorable mechanical properties. However, optomechanical devices require a vacuum environment to inhibit damping due to air.We present an integrated platform for cavity optomechanics using thermo-compression bonding of silicon caps to provide on-chip vacuum sealing. We demonstrate optomechanical coupling in a vacuum-sealed ring resonator implemented on the platform, either by modulation of the laser power or by using an electrostatic phase shifter in the ring.By enabling optomechanics on a standard platform, we aim to make the technology available to a wider user base.
15.	Edinger, Pierre, et al. (author) Vacuum-sealed silicon photonic MEMS tunable ring resonator with an independent control over coupling and phase 2023 In: Optics Express. - : Optica Publishing Group. - 1094-4087. ; 31:4, s. 6540-6551 Journal article (peer-reviewed)abstract Ring resonators are a vital element for filters, optical delay lines, or sensors in silicon photonics. However, reconfigurable ring resonators with low-power consumption are not available in foundries today. We demonstrate an add-drop ring resonator with the independent tuning of round-trip phase and coupling using low-power microelectromechanical (MEMS) actuation. At a wavelength of 1540 nm and for a maximum voltage of 40 V, the phase shifters provide a resonance wavelength tuning of 0.15 nm, while the tunable couplers can tune the optical resonance extinction ratio at the through port from 0 to 30 dB. The optical resonance displays a passive quality factor of 29 000, which can be increased to almost 50 000 with actuation. The MEMS rings are individually vacuum-sealed on wafer scale, enabling reliable and long-term protection from the environment. We cycled the mechanical actuators for more than 4 x 109 cycles at 100 kHz, and did not observe degradation in their response curves. On mechanical resonance, we demonstrate a modulation increase of up to 15 dB, with a voltage bias of 4 V and a peak drive amplitude as low as 20 mV.
16.	Fischer, Andreas C., 1982-, et al. (author) high aspect ratio tsvs fabricated by magnetic self-assembly of gold-coated nickel wires 2012 In: Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd. - : IEEE conference proceedings. - 9781467319652 ; , s. 541-547 Conference paper (peer-reviewed)abstract Three-dimensional (3D) integration is an emerging technologythat vertically interconnects stacked dies of electronics and/orMEMS-based transducers using through silicon vias (TSVs).TSVs enable the realization of devices with shorter signal lengths,smaller packages and lower parasitic capacitances, which can resultin higher performance and lower costs of the system. Inthis paper we demonstrate a new manufacturing technology forhigh-aspect ratio (> 8) through silicon metal vias using magneticself-assembly of gold-coated nickel rods inside etched throughsilicon-via holes. The presented TSV fabrication technique enablesthrough-wafer vias with high aspect ratios and superior electricalcharacteristics. This technique eliminates common issues inTSV fabrication using conventional approaches, such as the metaldeposition and via insulation and hence it has the potential to reducesignificantly the production costs of high-aspect ratio stateof-the-art TSVs for e.g. interposer, MEMS and RF applications.
17.	Fischer, Andreas C., 1982-, et al. (author) Integrating MEMS and ICs 2015 In: Microsystems & Nanoengineering. - : Springer Science and Business Media LLC. - 2055-7434. ; 1:1, s. 1-16 Review (peer-reviewed)abstract The majority of microelectromechanical system (MEMS) devices must be combined with integrated circuits (ICs) for operation in larger electronic systems. While MEMS transducers sense or control physical, optical or chemical quantities, ICs typically provide functionalities related to the signals of these transducers, such as analog-to-digital conversion, amplification, filtering and information processing as well as communication between the MEMS transducer and the outside world. Thus, the vast majority of commercial MEMS products, such as accelerometers, gyroscopes and micro-mirror arrays, are integrated and packaged together with ICs. There are a variety of possible methods of integrating and packaging MEMS and IC components, and the technology of choice strongly depends on the device, the field of application and the commercial requirements. In this review paper, traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed. These include approaches based on the hybrid integration of multiple chips (multi-chip solutions) as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques. These are important technological building blocks for the ‘More-Than-Moore’ paradigm described in the International Technology Roadmap for Semiconductors. In this paper, the various approaches are categorized in a coherent manner, their merits are discussed, and suitable application areas and implementations are critically investigated. The implications of the different MEMS and IC integration approaches for packaging, testing and final system costs are reviewed.
18.	Fischer, Andreas C., 1982-, et al. (author) Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic assembly of nickel wires 2012 In: Journal of Micromechanics and Microengineering. - : Institute of Physics (IOP). - 0960-1317 .- 1361-6439. ; 22:10, s. 105001- Journal article (peer-reviewed)abstract Through-silicon via (TSV) technology enables 3D-integrated devices with higher performance and lower cost as compared to 2D-integrated systems. This is mainly due to smaller dimensions of the package and shorter internal signal lengths with lower capacitive, resistive and inductive parasitics. This paper presents a novel low-cost fabrication technique for metal-filled TSVs with very high aspect ratios (>20). Nickel wires are placed in via holes of a silicon wafer by an automated magnetic assembly process and are used as a conductive path of the TSV. This metal filling technique enables the reliable fabrication of through-wafer vias with very high aspect ratios and potentially eliminates characteristic cost drivers in the TSV production such as advanced metallization processes, wafer thinning and general issues associated with thin-wafer handling.
19.	Grogg, Daniel, et al. (author) Amorphous carbon active contact layer for reliable nanoelectromechanical switches 2014 In: 2014 IEEE 27th International Conference on Micro Electro Mechanical Systems (MEMS). - : IEEE conference proceedings. - 9781479935086 ; , s. 143-146 Conference paper (peer-reviewed)abstract This paper reports an amorphous carbon (a-C) contact coating for ultra-low-ower curved nanoelectromechanical (NEM) switches. a-C addresses important problems in miniaturization and low-ower operation of mechanical relays: i) the surface energy is lower than that of metals, ii) active formation of highly localized a-C conducting filaments offers a way to form nanoscale contacts, and iii) high reliability is achieved through the excellent wear properties of a-C, demonstrated in this paper with more than 100 million hot switching cycles. Finally, a full inverter using a-C contacts is fabricated to demonstrate the viability of the concept.
20.	Jo, Gaehun, 1992-, et al. (author) Wafer-level Hermetic Sealing of Silicon Photonic MEMS by Direct Metal-to-Metal Bonding 2022 Conference paper (other academic/artistic)abstract The field of silicon (Si) photonic micro-electromechanical system (MEMS) for photonic integrated circuits (PICs) has evolved rapidly. Thanks to the ultra-low power consumption of Si photonic MEMS, it enables a wide range of high-performance photonic devices such as integrated optical MEMS phase shifters, tunable couplers and switches. However, photonic MEMS have suspended and movable parts which need to be protected from environmental influences, such as exposure to dust and humidity. Therefore, a packaging solution is needed for reliable operation over long periods. Here, we demonstrate wafer-level vacuum sealing of Si photonic MEMS inside cavities with ultra-thin Si caps.
21.	Jo, Gaehun, 1992-, et al. (author) Wafer-level hermetically sealed silicon photonic MEMS 2022 In: Photonics Research. - : Optical Society of America. - 2327-9125. ; 10:2, s. A14-A21 Journal article (peer-reviewed)abstract The emerging fields of silicon (Si) photonic micro–electromechanical systems (MEMS) and optomechanics enable a wide range of novel high-performance photonic devices with ultra-low power consumption, such as integrated optical MEMS phase shifters, tunable couplers, switches, and optomechanical resonators. In contrast to conventional SiO2-clad Si photonics, photonic MEMS and optomechanics have suspended and movable parts that need to be protected from environmental influence and contamination during operation. Wafer-level hermetic sealing can be a cost-efficient solution, but Si photonic MEMS that are hermetically sealed inside cavities with optical and electrical feedthroughs have not been demonstrated to date, to our knowledge. Here, we demonstrate wafer-level vacuum sealing of Si photonic MEMS inside cavities with ultra-thin caps featuring optical and electrical feedthroughs that connect the photonic MEMS on the inside to optical grating couplers and electrical bond pads on the outside. We used Si photonic MEMS devices built on foundry wafers from the iSiPP50G Si photonics platform of IMEC, Belgium. Vacuum confinement inside the sealed cavities was confirmed by an observed increase of the cutoff frequency of the electro-mechanical response of the encapsulated photonic MEMS phase shifters, due to reduction of air damping. The sealing caps are extremely thin, have a small footprint, and are compatible with subsequent flip-chip bonding onto interposers or printed circuit boards. Thus, our approach for sealing of integrated Si photonic MEMS clears a significant hurdle for their application in high-performance Si photonic circuits.
22.	Jo, Gaehun, 1992-, et al. (author) Wafer-Level Vacuum Sealing for Packaging of Silicon Photonic MEMS 2021 In: Proceedings SPIE OPTO 6-12 march 2021 silicon photonics XVI. - : SPIE-Intl Soc Optical Eng. Conference paper (other academic/artistic)abstract Silicon (Si) photonic micro-electro-mechanical systems (MEMS), with its low-power phase shifters and tunable couplers, is emerging as a promising technology for large-scale reconfigurable photonics with potential applications for example in photonic accelerators for artificial intelligence (AI) workloads. For silicon photonic MEMS devices, hermetic/vacuum packaging is crucial to the performance and longevity, and to protect the photonic devices from contamination. Here, we demonstrate a wafer-level vacuum packaging approach to hermetically seal Si photonic MEMS wafers produced in the iSiPP50G Si photonics foundry platform of IMEC. The packaging approach consists of transfer bonding and sealing the silicon photonic MEMS devices with 30 µm-thick Si caps, which were prefabricated on a 100 mm-diameter silicon-on-insulator (SOI) wafer. The packaging process achieved successful wafer-scale vacuum sealing of various photonic devices. The functionality of photonic MEMS after the hermetic/vacuum packaging was confirmed. Thus, the demonstrated thin Si cap packaging shows the possibility of a novel vacuum sealing method for MEMS integrated in standard Si photonics platforms.
23.	Khan, Umar, et al. (author) Low power actuators for programmable photonic processors 2023 In: AI and Optical Data Sciences IV. - : SPIE-Intl Soc Optical Eng. Conference paper (peer-reviewed)abstract The demand for efficient actuators in photonics has peaked with increasing popularity for large-scale general-purpose programmable photonics circuits. We present our work to enhance an established silicon photonics platform with low-power micro-electromechanical (MEMS) and liquid crystal (LC) actuators to enable large-scale programmable photonic integrated circuits (PICs).
24.	Khan, Umar, et al. (author) MORPHIC : MEMS enhanced silicon photonics for programmable photonics 2022 In: Integrated Photonics Platforms Ii. - : SPIE-Intl Soc Optical Eng. Conference paper (peer-reviewed)abstract We present our work in the European project MORPHIC to extend an established silicon photonics platform with low-power and non-volatile micro-electromechanical (MEMS) actuators to demonstrate large-scale programmable photonic integrated circuits (PICs).
25.	Kulsreshath, Mukesh K., et al. (author) Digital Nanoelectromechanical Non-Volatile Memory Cell 2024 In: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 45:4, s. 728-731 Journal article (peer-reviewed)abstract Nanoelectromechanical relays are inherently radiation hard and can operate at high temperatures. Thus, they have potential to serve as the building blocks in non-volatile memory that can be used in harsh environments with zero standby power. However, a reprogrammable memory cell built entirely from relays that can be operated with a digital protocol has not yet been demonstrated. Here, we demonstrate a fully mechanical digital non-volatile memory cell built from in-plane silicon nanoelectromechanical relays; a 7-terminal bistable relay utilizes surface adhesion forces to store binary data without consuming any energy, while 3-terminal relays are used for read and write access without the need for CMOS. We have optimized the designs to prevent collapse to the substrate under actuation and recorded voltages of 13, 13.2 and 27V for programming, read and reprogramming operations. This non-volatile memory cell can potentially be used to build embedded memories for edge applications that have stringent temperature, radiation and energy constraints.
26.	Laakso, Miku, 1989-, et al. (author) Through-Glass Vias for MEMS Packaging 2018 Conference paper (other academic/artistic)abstract Novelty / Progress Claims We have developed a new method for fabrication of through-glass vias (TGVs). The method allows rapid filling of via holes with metal rods both in thin and thick glass substrates.Background Vertical electrical feedthroughs in glass substrates, i.e. TGVs, are often required in wafer-scale packaging of MEMS that utilizes glass lids. The current methods of making TGVs have drawbacks that prevent the full utilization of the excellent properties of glass as a package material, e.g. low RF losses. Magnetic assembly has been used earlier to fabricate through-silicon vias (TSVs), and in this work we extend this method to realize TGVs [1]. Methods The entire TGV fabrication process is maskless, and the processes used include: direct patterning of wafer metallization using femtosecond laser ablation, magnetic-fieldassisted self-assembly of metal wires into via holes, and solder-paste jetting of bump bonds on TGVs.Results We demonstrate that: (1) the magnetically assembled TGVs have a low resistance, which makes them suitable even for low-loss and high-current applications; (2) the magneticassembly process can be parallelized in order to increase the wafer-scale fabrication speed; (3) the magnetic assembly produces void-free metal filling for TGVs, which allows solder placement directly on top of the TGV for the purpose of high integration density; and (4) good thermal-expansion compatibility between TGV metals and glass substrates is possible with the right choice of materials, and several suitable metals-glass pairs are identified for possible improvement of package reliability [2].[1] M. Laakso et al., IEEE 30th Int. Conf. on MEMS, 2017. DOI:10.1109/MEMSYS.2017.7863517[2] M. Laakso et al., “Through-Glass Vias for Glass Interposers and MEMS Packaging Utilizing Magnetic Assembly of Microscale Metal Wires,” manuscript in preparatio
27.	Li, Yingying, 1994-, et al. (author) Design and fabrication of a 4-terminal in-plane nanoelectromechanical relay 2023 Conference paper (peer-reviewed)abstract We present 4-terminal (4-T) silicon (Si) nanoelectronmechanical (NEM) relays fabricated on silicon-oninsulator (SOI) wafers. We demonstrate true 4-T switching behavior with isolated control and signal paths. A pull-in voltage as low as 11.6 V is achieved with the miniaturized design. 4-T NEM relays are a very promising candidate for building ultra-low-power logic circuits since they enable novel circuit architectures to realize logic functions with far fewer devices than CMOS implementations, while also allowing the dynamic power consumption to be reduced by body-biasing.
28.	Li, Yingying, 1994-, et al. (author) Integrated 4-terminal single-contact nanoelectromechanical relays implemented in a silicon-on-insulator foundry process 2023 In: Nanoscale. - : Royal Society of Chemistry. - 2040-3364 .- 2040-3372. Journal article (peer-reviewed)abstract Integrated nanoelectromechanical (NEM) relays can be used instead of transistors to implement ultra-low power logic circuits, due to their abrupt turn-off characteristics and zero off-state leakage. Further, realizing circuits with 4-terminal (4-T) NEM relays enables significant reduction in circuit device count compared to conventional transistor circuits. For practical 4-T NEM circuits, however, the relays need to be miniaturized and integrated with high-density back-end-of-line (BEOL) interconnects, which is challenging and has not been realized to date. Here, we present electrostatically actuated silicon 4-T NEM relays that are integrated with multi-layer BEOL metal interconnects, implemented using a commercial silicon-on-insulator (SOI) foundry process. We demonstrate 4-T switching and the use of body-biasing to reduce pull-in voltage of a relay with a 300 nm airgap, from 15.8 V to 7.8 V, consistent with predictions of the finite-element model. Our 4-T NEM relay technology enables new possibilities for realizing NEM-based circuits for applications demanding harsh environment computation and zero standby power, in industries such as automotive, Internet-of-Things, and aerospace.
29.	Niklaus, Frank, et al. (author) Wafer-level heterogeneous 3D integration for MEMS and NEMS 2012 In: Proceedings of 2012 3rd IEEE International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2012. - : IEEE conference proceedings. - 9781467307420 ; , s. 247-252 Conference paper (peer-reviewed)abstract In this paper the state-of-the-art in wafer-level heterogeneous 3D integration technologies for micro-electromechanical systems (MEMS) and nano-electromechanical systems (NEMS) is reviewed. Various examples of commercial and experimental heterogeneous 3D integration processes for MEMS and NEMS devices are presented and discussed.
30.	Pamunuwa, Dinesh, et al. (author) Hardware Platform for Edge Computing Based on Nanoelectromechanical Relays 2023 In: 2023 22nd International Conference on Solid-State Sensors, Actuators and Microsystems, Transducers 2023. - : Institute of Electrical and Electronics Engineers Inc.. ; , s. 537-541 Conference paper (peer-reviewed)abstract NEM relay-based circuits can operate in harsh environmental conditions, high temperatures and high levels of radiation, without consuming energy in standby mode. These attributes make NEM relay technology very attractive for edge computing applications in industrial and manufacturing sectors. Here we describe a complete hardware platform for designing and fabricating densely integrated NEM relay circuits, and discuss the design of several prototypes we are developing to showcase this technology.
31.	Qin, Tian, et al. (author) Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays 2018 In: IEEE Access. - : Institute of Electrical and Electronics Engineers (IEEE). - 2169-3536. ; 6, s. 15997-16009 Journal article (peer-reviewed)abstract The energy consumption of field-programmable gate arrays (FPGA) is dominated by leakage currents and dynamic energy associated with programmable interconnect. An FPGA built entirely from nanoelectromechanical (NEM) relays can effectively eliminate leakage energy losses, reduce the interconnect dynamic energy, operate at temperatures >225 °C and tolerate radiation doses in excess of 100 Mrad, while hybrid FPGAs comprising both complementary metal-oxide-semiconductor (CMOS) transistors and NEM relays (NEM-CMOS) have the potential to realize improvements in performance and energy efficiency. Large-scale integration of NEM relays, however, poses a significant engineering challenge due to the presence of moving parts. We discuss the design of FPGAs utilizing NEM relays based on a heterogeneous 3-D integration scheme, and carry out a scaling study to quantify key metrics related to performance and energy efficiency in both NEM-only and NEM-CMOS FPGAs. We show how the integration scheme has a profound effect on these metrics by changing the length of global wires. The scaling regime beyond which net performance and energy benefits is seen in NEM-CMOS over a baseline 90 nm CMOS technology is defined by an effective relay beam length of 0.5 μm , on-resistance of 200 kΩ , and a via pitch of 0.4 μm , all achievable with existing process technology. For ultra-low energy applications that are not performance critical, NEM-only FPGAs can provide close to 15× improvement in energy efficiency.
32.	Quack, Niels, et al. (author) Integrated silicon photonic MEMS 2023 In: MICROSYSTEMS & NANOENGINEERING. - : Springer Nature. - 2055-7434. ; 9:1 Journal article (peer-reviewed)abstract Silicon photonics has emerged as a mature technology that is expected to play a key role in critical emerging applications, including very high data rate optical communications, distance sensing for autonomous vehicles, photonic-accelerated computing, and quantum information processing. The success of silicon photonics has been enabled by the unique combination of performance, high yield, and high-volume capacity that can only be achieved by standardizing manufacturing technology. Today, standardized silicon photonics technology platforms implemented by foundries provide access to optimized library components, including low-loss optical routing, fast modulation, continuous tuning, high-speed germanium photodiodes, and high-efficiency optical and electrical interfaces. However, silicon's relatively weak electro-optic effects result in modulators with a significant footprint and thermo-optic tuning devices that require high power consumption, which are substantial impediments for very large-scale integration in silicon photonics. Microelectromechanical systems (MEMS) technology can enhance silicon photonics with building blocks that are compact, low-loss, broadband, fast and require very low power consumption. Here, we introduce a silicon photonic MEMS platform consisting of high-performance nano-opto-electromechanical devices fully integrated alongside standard silicon photonics foundry components, with wafer-level sealing for long-term reliability, flip-chip bonding to redistribution interposers, and fibre-array attachment for high port count optical and electrical interfacing. Our experimental demonstration of fundamental silicon photonic MEMS circuit elements, including power couplers, phase shifters and wavelength-division multiplexing devices using standardized technology lifts previous impediments to enable scaling to very large photonic integrated circuits for applications in telecommunications, neuromorphic computing, sensing, programmable photonics, and quantum computing.
33.	Rana, Sunil, et al. (author) Nanoelectromechanical relay without pull-in instability for high-temperature non-volatile memory 2020 In: Nature Communications. - : Nature Publishing Group. - 2041-1723. ; 11:1 Journal article (peer-reviewed)abstract Emerging applications such as the Internet-of-Things and more-electric aircraft require electronics with integrated data storage that can operate in extreme temperatures with high energy efficiency. As transistor leakage current increases with temperature, nanoelectromechanical relays have emerged as a promising alternative. However, a reliable and scalable non-volatile relay that retains its state when powered off has not been demonstrated. Part of the challenge is electromechanical pull-in instability, causing the beam to snap in after traversing a section of the airgap. Here we demonstrate an electrostatically actuated nanoelectromechanical relay that eliminates electromechanical pull-in instability without restricting the dynamic range of motion. It has several advantages over conventional electrostatic relays, including low actuation voltages without extreme reduction in critical dimensions and near constant actuation airgap while the device moves, for improved electrostatic control. With this nanoelectromechanical relay we demonstrate the first high-temperature non-volatile relay operation, with over 40 non-volatile cycles at 200 °C.
34.	Wang, Xiaojing, et al. (author) Narrow footprint copper sealing rings for low-temperature hermetic wafer-level packaging 2017 In: TRANSDUCERS 2017 - 19th International Conference on Solid-State Sensors, Actuators and Microsystems. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781538627310 ; , s. 423-426 Conference paper (peer-reviewed)abstract This paper reports a narrow footprint sealing ring design for low-temperature, hermetic, and mechanically stable wafer-level packaging. Copper (Cu) sealing rings that are as narrow as 8 μm successfully seal the enclosed cavities on the wafers after bonding at a temperature of 250 °C. Different sealing structure designs are evaluated and demonstrate excellent hermeticity after 3 months of storage in ambient atmosphere. A leak rate of better than 3.6×10'16 mbarL/s is deduced based on results from residual gas analysis measurements. The sealing yield after wafer bonding is found to be not limited by the Cu sealing ring width but by a maximum acceptable wafer-to-wafer misalignment.
35.	Wang, Xiaojing, 1990-, et al. (author) Wafer-level vacuum packaging enabled by plastic deformation and low-temperature welding of copper sealing rings with a small footprint 2017 In: Journal of microelectromechanical systems. - : IEEE. - 1057-7157 .- 1941-0158. ; 26:2, s. 357-365 Journal article (peer-reviewed)abstract Wafer-level vacuum packaging is vital in the fabrication of many microelectromechanical systems (MEMS) devices and enables significant cost reduction in high-volume MEMS production. In this paper, we propose a low-temperature wafer-level vacuum packaging method based on plastic deformation and low-temperature welding of copper sealing rings with a small footprint. A device wafer with copper ring structures and a cap wafer with corresponding metalized grooves are placed inside a vacuum chamber and pressed together at a temperature of 250 ̊C, resulting in low-temperature welding of the copper, and thus, hermetic sealing of the cavities enclosed by the sealing rings. The vacuum pressure inside the fabricated cavities 146 days after bonding was measured using residual gas analysis to be as low as 2.6×10-2 mbar. Based on this value, the leak rate is calculated to be smaller than 3.6×10-16 mbarL/s using the most conservative assumptions, demonstrating the excellent hermeticity of the seals. Shear testing was used to demonstrate that the seals are mechanically stable with over 90 MPa in shear strength for 5.2 μm-high Cu sealing rings with widths down to 8 μm. The reported method is potentially compatible with complementary metaloxide-semiconductor (CMOS) substrates and may be applied to vacuum packaging of 3-D heterogeneously integrated MEMS on state-of-the-art CMOS substrates.
36.	Wang, Xiaojing, 1990-, et al. (author) Wafer-Level Vacuum Sealing by Transfer Bonding of Silicon Caps for Small Footprint and Ultra-Thin MEMS Packages 2019 In: Journal of microelectromechanical systems. - 1057-7157 .- 1941-0158. ; 28:3, s. 460-471 Journal article (peer-reviewed)abstract Vacuum and hermetic packaging is a critical requirement for optimal performance of many micro-electro-mechanical systems (MEMS), vacuum electronics, and quantum devices. However, existing packaging solutions are either elaborate to implement or rely on bulky caps and footprint-consuming seals. Here, we address this problem by demonstrating a wafer-level vacuum packaging method featuring transfer bonding of 25-μm-thin silicon (Si) caps that are transferred from a 100-mm-diameter silicon-on-insulator (SOI) wafer to a cavity wafer to seal the cavities by gold-aluminum (Au-Al) thermo-compression bonding at a low temperature of 250 °C. The resulting wafer-scale sealing yields after wafer dicing are 98% and 100% with sealing rings as narrow as 6 and 9 μm, respectively. Despite the small sealing footprint, the Si caps with 9-μm-wide sealing rings demonstrate a high mean shear strength of 127 MPa. The vacuum levels in the getter-free sealed cavities are measured by residual gas analysis to be as low as 1.3 mbar, based on which a leak rate smaller than 2.8x10-14 mbarL/s is derived. We also show that the thickness of the Si caps can be reduced to 6 μm by post-transfer etching while still maintaining excellent hermeticity. The demonstrated ultra-thin packages can potentially be placed in between the solder bumps in flip-chip interfaces, thereby avoiding the need of through-cap-vias in conventional MEMS packages.

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